Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.

Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.

Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Abstract: A system for inserting a supplemental micro-operation sequence into a macroinstruction-generated micro-operation flow provides a versatile, flexible mechanism for early pipeline stages of a microprocessor to pass control signals, data, and other information to later pipeline stages. The mechanism is useful to maintain precise timing of a fault model in pipelined processors. A method includes the step of detecting the occurrence of a predetermined uop-inserting event and, responsive thereto, generating a control signal to a uop insertion unit. Responsive thereto, the uop insertion unit supplies signals to a decoder which, responsive thereto, decodes the signal encoded within the signal to provide the inserted uop sequence, which is inserted in a position within the macroinstruction-generated micro-operation flow predetermined by the uop-inserting event.

Abstract: A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.