Patents by Inventor Gustavo A. Pinto

Gustavo A. Pinto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940352
    Abstract: A system for detecting the watertightness or flooding of an annulus of flexible lines from a connector. The system includes: an assembly of plunger and cylinder that are connected by a rod to a chamber that acts as a pilot valve. The assembly is connected directly to the outlet of a safety valve of a connector of the flexible line, in which same are fitted using a sealing system. The system is operated by commands sent to a ROV that has an arm and that controls the system using a handle.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 26, 2024
    Assignee: Petróleo Brasileiro S.A.—Petrobras
    Inventors: Paulo Roberto Santos Poli, Joao Marcio De Castilho Santos, Gustavo Pinto Pires, Cassio Kuchpil, Carlos Eduardo Maia De Souza
  • Publication number: 20220215133
    Abstract: Techniques regarding manufacturing a desired product from a digital product design are provided. For example, one or more embodiments described herein can regard a system, which can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a build package component that canonicalizes manufacturing inputs regarding a product design into a digital build package that enables portability of manufacturing the product design within a network of manufacturing facilities, wherein the digital build package delineates how the product design is to be manufactured and references a computer-aided design file that characterizes the product design.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 7, 2022
    Inventors: William Paul King, Timothy Gossett, Gustavo Pinto, Aaron Vincent Brenzel, Louis William Rassey, Charles D. Wood, John William Nanry
  • Publication number: 20220214666
    Abstract: Techniques regarding manufacturing one or more digital product designs are provided. For example, one or more embodiments described herein can include a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a user interface component that generates a manufacturability report regarding a product design in relation to a manufacturing process. The manufacturability report can indicate whether a product feature included in the product design is permissible based on a plurality of manufacturing considerations associated with the manufacturing process.
    Type: Application
    Filed: August 30, 2021
    Publication date: July 7, 2022
    Inventors: William Paul King, Dan Michael Arwine, Aaron Vincent Brenzel, Kent Green, Clark Kampfe, Patrick McCusker, John William Nanry, Max Newberger, David Pick, Gustavo Pinto, Louis William Rassey, Duru Turkoglu, Matthew Weckel, Charles D. Wood, Rory Eugene Hartong-Redden, Timothy Gossett
  • Publication number: 20220214667
    Abstract: Techniques regarding manufacturing one or more digital product designs are provided. For example, one or more embodiments described herein can include a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a user interface component that generates a manufacturability report regarding a product design in relation to a manufacturing process. The manufacturability report can indicate whether a product feature included in the product design is permissible based on a plurality of manufacturing considerations associated with the manufacturing process.
    Type: Application
    Filed: August 30, 2021
    Publication date: July 7, 2022
    Inventors: William Paul King, Dan Michael Arwine, Aaron Vincent Brenzel, Kent Green, Clark Kampfe, Patrick McCusker, John William Nanry, Max Newberger, David Pick, Gustavo Pinto, Louis William Rassey, Duru Turkoglu, Matthew Weckel, Charles D. Wood, Rory Eugene Hartong-Redden, Timothy Gossett
  • Publication number: 20220214668
    Abstract: Techniques regarding manufacturing one or more digital product designs are provided. For example, one or more embodiments described herein can include a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a user interface component that generates a manufacturability report regarding a product design in relation to a manufacturing process. The manufacturability report can indicate whether a product feature included in the product design is permissible based on a plurality of manufacturing considerations associated with the manufacturing process.
    Type: Application
    Filed: August 30, 2021
    Publication date: July 7, 2022
    Inventors: William Paul King, Dan Michael Arwine, Aaron Vincent Brenzel, Kent Green, Clark Kampfe, Patrick McCusker, John William Nanry, Max Newberger, David Pick, Gustavo Pinto, Louis William Rassey, Duru Turkoglu, Matthew Weckel, Charles D. Wood, Rory Eugene Hartong-Redden, Timothy Gossett
  • Publication number: 20220128512
    Abstract: This invention provides a system for detecting flooding in a flexible pipe from a connector of the flexible pipe, comprising: an ROV (3) comprising an arm element (18) designed to move an ultrasound sensor (13), until the ultrasound sensor (13) comes into contact with the connector (14) of the flexible pipe (17); and means for taking ultrasound measurements with respect to the state of the annulus of the flexible pipe (17) from a chamber of the connector of the flexible pipe (17) in contact with the annulus of the flexible pipe (17).
    Type: Application
    Filed: September 20, 2019
    Publication date: April 28, 2022
    Applicant: PETRÓLEO BRASILEIRO S.A. - PETROBRAS
    Inventors: Paulo Roberto SANTOS POLI, Nei Mariano DA FONSECA JUNIOR, Marco Antonio DA SILVA, João Marcio DE CASTILHO SANTOS, Gustavo PINTO PIRES, Carlos Eduardo MAIA DE SOUZA
  • Publication number: 20220034747
    Abstract: The present invention relates to a system for detecting the watertightness or flooding of the annulus of flexible lines from a connector, comprising: an assembly of plunger (3) and cylinder (4) that are connected by a rod to a chamber (19) that acts as a pilot valve, connected directly to the outlet of a safety valve of a connector of the flexible line, in which same are fitted using a sealing system (6). The system is operated by commands sent to the ROV (2) that has an arm (21) and that controls the system using a handle (9). The present invention also describes the operating method of the device and how the obtained results lead to a preprogrammed conclusion regarding the watertightness (or otherwise) of the annulus. Other methods are provided to obtain fluid samples in the annulus for subsequent analysis and enable the safety valve to be removed from the connectors.
    Type: Application
    Filed: December 2, 2019
    Publication date: February 3, 2022
    Inventors: Paulo Roberto SANTOS POLI, Joao Marcio DE CASTILHO SANTOS, Gustavo PINTO PIRES, Cassio KUCHPIL, Carlos Eduardo MAIA DE SOUZA
  • Publication number: 20140315332
    Abstract: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventors: Gustavo A. Pinto, Tony P. Chiang, Kurt H. Weiner
  • Patent number: 8772772
    Abstract: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: July 8, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Kurt H. Weiner, Tony P. Chiang, Gustavo A. Pinto
  • Patent number: 7655482
    Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 2, 2010
    Assignee: KLA-Tencor
    Inventors: Akella V. S. Satya, Lynda C. Mantalas, Gustavo A. Pinto
  • Patent number: 7656170
    Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: February 2, 2010
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V. S. Satya, Padma A. Satya, legal representative, Robert Thomas Long, David J. Walker
  • Publication number: 20080246030
    Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
    Type: Application
    Filed: February 14, 2007
    Publication date: October 9, 2008
    Inventors: Akella V.S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas, Padma A. Satya
  • Publication number: 20080237487
    Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
    Type: Application
    Filed: February 14, 2007
    Publication date: October 2, 2008
    Inventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V.S. Satya, Robert Thomas Long, David J. Walker, Padma A. Satya
  • Publication number: 20070267631
    Abstract: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 22, 2007
    Applicant: Intermolecular, Inc.
    Inventors: Kurt H. Weiner, Tony P. Chiang, Gustavo A. Pinto
  • Publication number: 20070202610
    Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Inventors: Tony Chiang, David Lazovsky, Kurt Weiner, Gustavo Pinto, Thomas Boussie, Alexander Gorer
  • Publication number: 20070202614
    Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Inventors: Tony Chiang, David Lazovsky, Kurt Weiner, Gustavo Pinto, Thomas Boussie, Alexander Gorer
  • Publication number: 20070111342
    Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
    Type: Application
    Filed: January 9, 2007
    Publication date: May 17, 2007
    Inventors: Akella Satya, Lynda Mantalas, Gustavo Pinto
  • Patent number: 7179661
    Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: February 20, 2007
    Assignee: KLA-Tencor
    Inventors: Akella V. S. Satya, Lynda C. Mantalas, Gustavo A. Pinto
  • Publication number: 20060292846
    Abstract: Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of the processing. Information or data of the transferred materials is automatically captured during the transfer events. Processing systems described include at least one identification (ID) device coupled to the subsystems. A data device is coupled to the ID device and to a device that performs the material transfers. The data device is configured to send or receive identification information of the subsystems from the ID device, and to send or receive information of transferred material from the material handling device.
    Type: Application
    Filed: May 5, 2006
    Publication date: December 28, 2006
    Inventors: Gustavo Pinto, Tony Chiang
  • Publication number: 20060119977
    Abstract: A system and methods for efficiently performing media writing functions is disclosed. The system and methods include: detecting media movement with respect to a base and heads during reading and writing, and moving the heads in response; using an interferometer, such as a dual beam differential interferometer, to dynamically monitor disk position and address perceived errors; and minimizing repeatable and non repeatable runout error by writing data, such as servo bursts, in multiple revolutions to average adverse runout conditions. The present system has the ability to use an interferometer to enhance media certification and perform on line, in situ monitoring of the media, and includes shrouding, head mounting, disk biasing, and related mechanical aspects beneficial to media writing.
    Type: Application
    Filed: September 28, 2005
    Publication date: June 8, 2006
    Inventors: Jun Zhu, Alex Moraru, Teodor Zanetti, Franklin Tao, Dan Kilmer, Harald Hess, Tom Carr, Matt Bellis, Gustavo Pinto, Patrick Lee