Abstract: One or more line ends of a putative integrated circuit design are modelled using a constraint graph. A longest path algorithm is applied on subgraphs of the constraint graph. An extent minimization algorithm is carried out on the subgraphs of the constraint graph and routing on the putative integrated circuit design is carried out based on results of the longest path algorithm and the extent minimization algorithm.

Abstract: A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

Abstract: Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program (“ILP”) operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

Abstract: Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Abstract: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Abstract: Aspects of the invention include systems and methods for implementing a sweepline triangulation technique to optimize spanning graphs for circuit routing. A non-limiting example computer-implemented method includes receiving an unrouted net having a plurality of elements. The elements can include pins, vias, and wires. A sweepline is passed across the unrouted net until the sweepline intersects an element of the plurality of elements. In response to the sweepline intersecting the element, the sweepline is stopped and one or more nodes on the sweepline and one or more previous nodes are identified. A connectivity graph is built from the one or more nodes and the one or more previous nodes. The connectivity graph includes one or more arcs and one or more guides. A minimum spanning tree is built by removing one or more guides from the connectivity graph and the unrouted net is routed based on the minimum spanning tree.

Abstract: Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Abstract: Aspects of the invention include systems and methods for implementing a sweepline triangulation technique to optimize spanning graphs for circuit routing. A non-limiting example computer-implemented method includes receiving an unrouted net having a plurality of elements. The elements can include pins, vias, and wires. A sweepline is passed across the unrouted net until the sweepline intersects an element of the plurality of elements. In response to the sweepline intersecting the element, the sweepline is stopped and one or more nodes on the sweepline and one or more previous nodes are identified. A connectivity graph is built from the one or more nodes and the one or more previous nodes. The connectivity graph includes one or more arcs and one or more guides. A minimum spanning tree is built by removing one or more guides from the connectivity graph and the unrouted net is routed based on the minimum spanning tree.

Abstract: A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

Abstract: Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Abstract: One or more line ends of a putative integrated circuit design are modelled using a constraint graph. A longest path algorithm is applied on subgraphs of the constraint graph. An extent minimization algorithm is carried out on the subgraphs of the constraint graph and routing on the putative integrated circuit design is carried out based on results of the longest path algorithm and the extent minimization algorithm.

Abstract: Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.

Abstract: Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: A method of performing physical design of an integrated circuit includes subdividing each metal layer of a plurality of metal layers of the integrated circuit into a plurality of g-cells. Each metal layer has either horizontal or vertical tracks, the g-cells of the metal layers with horizontal tracks have vertical edges between adjacent ones of the g-cells, and the g-cells of the metal layers with vertical tracks have horizontal edges between adjacent ones of the g-cells. The method includes determining congestion for each metal layer as congestion values associated with the horizontal edges or the vertical edges of the metal layer, identifying hotspots for each metal layer based on the congestion values of the metal layer, determining a penalty associated with the hotspots of each metal layer, determining a congestion metric for each metal layer based on the penalty, and performing routing of the wires based on the congestion metric.

Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.

Abstract: A method of performing physical design of an integrated circuit includes subdividing each metal layer of a plurality of metal layers of the integrated circuit into a plurality of g-cells. Each metal layer has either horizontal or vertical tracks, the g-cells of the metal layers with horizontal tracks have vertical edges between adjacent ones of the g-cells, and the g-cells of the metal layers with vertical tracks have horizontal edges between adjacent ones of the g-cells. The method includes determining congestion for each metal layer as congestion values associated with the horizontal edges or the vertical edges of the metal layer, identifying hotspots for each metal layer based on the congestion values of the metal layer, determining a penalty associated with the hotspots of each metal layer, determining a congestion metric for each metal layer based on the penalty, and performing routing of the wires based on the congestion metric.

Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.