Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or “puck” disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface.

Abstract: A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.

Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or “puck” disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface.

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate.

Abstract: A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

Abstract: A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

Abstract: A method for controlling the voltage distribution of the standing wave impressed upon the coil of an inductively coupled plasma generator includes the steps of impressing a radio frequency voltage across the coil to establish a standing wave thereacross. A voltage profile is selected for the standing wave so as to control the location and amount of capacitive coupling. A circuit parameter is controlled to achieve the selected voltage profile. Proper selection of the voltage profile enhances process capabilities, decreases the time between cleans, minimizes component wear, and minimizes cleaning time. An apparatus for carrying out the disclosed method is also disclosed.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or "puck" disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate.

Abstract: A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, an apparatus for controlling the planarizing characteristics of a microelectronic substrate has a carrier that may be positioned with respect to a polishing medium of a planarizing machine to move with respect to a microelectronic substrate during planarization. The apparatus may also have a modulator with a contact element, and the modulator may be attached to the carrier to position at least a portion of a contact element in front of a leading edge of the substrate by a selected distance during planarization. In operation, the modulator causes the contact element to selectively engage a region of the planarizing surface to modulate the contour of the planarizing surface during planarization.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A plasma reactor includes, a) an electrically insulative shell forming a reactor cavity, the reactor cavity having internal walls; b) inductive coils positioned externally of the cavity; and c) a capacitive coupling plate positioned externally of the cavity intermediate the cavity and inductive coils, a power source being operably connected with the capacitive coupling plate. A method of cleaning away material adhering to internal walls of a plasma reactor includes, a) injecting a cleaning gas into the reactor, the cleaning gas comprising a species which when ionized is reactive with material adhering to the internal plasma reactor walls; and b) generating a capacitive coupling effect between a pair of conductors, at least one of which is positioned externally of the plasma reactor, effective to both ionize the cleaning gas into the reactive ionized species and draw such ionized species in the direction of the external conductor to impact and clean away material adhering to the reactor internal walls.

Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or "puck" disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer ensuring the formation of a high quality planar surface.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.