Abstract: Multiple memory access streams issued by multiple memory controller access devices are used for accessing DRAM or other memory. The memory controller can arbitrate among requests for multiple requestors, such as in a multiprocessor environment. Coherency can be provided by snooping a write buffer and returning, write buffer contents directly, in response to a read request for a matching address. Coherency need not be implemented through the entirety of an address space and preferably can be enabled for only selected portion or portions of the address space, reducing unnecessary coherency checking overhead.

Abstract: A multicast engine of a shared-memory switching fabric circuit increases the replication rate of data elements destined for multicast connections within a network switch by manipulating address information relating to those elements. The multicast engine cooperates with other components of the switching fabric circuit to minimize the total buffer requirements of the switch by storing only a single copy of each multicast data element in a location of shared memory. Specifically, the engine has a pipelined architecture that provides a multicasting capability for the switching fabric circuit by replicating only an address pointer to that memory location for each destination of the multicast connection.

Abstract: The present invention provides a system for supporting one or more memory requestors (CPU's and I/O DMA) accessing a plurality of DRAM memory banks. The present invention is a multiplexer that functions as a 16-bit slice of the interface between the CPU and a 64-bit slice of DRAM memory array. The invention includes an error correction (ECC) module, a 64-bit DRAM I/O channel, an 8-bit ECC "syndrome" I/O channel and an 8-bit slice of a DMA bus I/O channel. In a write operation, the CPU transmits data through the I/O channel to write the data to the DRAM. Each word is routed by the four-way multiplexer to one of the four memory registers. When the four registers have been filled with data words, the words are assembled into a multiple word burst and sent to the DRAM bank. The data is also passed through an error correction module. For a read operation, DRAM data is latched into the CPU register and transported to the CPU while the DRAM is potentially being accessed for another memory read.