Abstract: The present invention is directed to a process for making Substituted Quinazoline Compounds of formula (I): which are useful for the treatment and prophylaxis of HCMV infection. The present invention is also directed to compounds that are useful as synthetic intermediates for making the compounds of formula (I).

Abstract: This invention describes an amidation process whereby perfluorinated amino acids can be activated and treated with an amine in the presence of a coupling agent and a pyridine derivative to yield amides, without loss of optical purity.

Abstract: The present invention is directed to a process for making Substituted Quinazoline Compounds of formula (I): which are useful for the treatment and prophylaxis of HCMV infection. The present invention is also directed to compounds that are useful as synthetic intermediates for making the compounds of formula (I).

Abstract: This invention describes an amidation process whereby perfluorinated amino acids can be activated and treated with an amine in the presence of a coupling agent and a pyridine derivative to yield amides, without loss of optical purity.

Abstract: The present invention includes compounds useful as intermediates in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing macrolactams from the intermediates. One use of the methods and intermediates described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity. HCV NS3 inhibitory compounds have therapeutic and research applications.

Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: The present invention relates to macrolactam compounds, intermediates useful in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing and modifying macrolactams. One use of the compounds and methods described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity. An example of an HCV inhibitory compound that can be synthesized using the procedures described herein is Compound A and derivative thereof.

Abstract: A first aspect of the present invention describes a compound selected from group consisting of: wherein R is either H, C(O)RA, or C(O)NHCH(X)COOH; provided that X is a C2-C6 alkyl, or a C3-C8 cycloalkyl and RA is a C1-6 alkyl or aryl; These compounds are used to make Compound A

Abstract: The instant invention describes a novel asymmetric synthesis of fluoroleucine alkyl esters which utilizes a phase transfer catalyst and a solid additive.

Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: The present invention includes compounds useful as intermediates in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing macrolactams. One use of the methods and intermediates described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity.

Abstract: The present invention includes compounds useful as intermediates in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing macrolactams from the intermediates. One use of the methods and intermediates described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity. HCV NS3 inhibitory compounds have therapeutic and research applications.

Abstract: This invention describes an amidation process whereby perfluorinated amino acids can be activated and treated with an amine in the presence of a coupling agent and a pyridine derivative to yield amides, without loss of optical purity.

Abstract: The present invention relates to macrolactam compounds, intermediates useful in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing and modifying macrolactams. One use of the compounds and methods described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity. An example of an HCV inhibitory compound that can be synthesized using the procedures described herein is Compound A and derivative thereof.

Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

Abstract: A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Abstract: A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

Abstract: A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Abstract: A CMOS buffer with hysteresis is implemented. In one embodiment, an upper-trip circuit (102) and a lower-trip circuit (104) are implemented with CMOS inverters. The upper-trip circuit (102) and the lower-trip circuit (104) provides output to a pull-up device (110) and a pull-down device (111), respectively. The pull-up device (110) and the pull-down device (111) both generate an output signal onto a net (112). A bus holder (114) is coupled to the net (112) and maintains the output signal. In addition, an output circuit (116) is coupled to the net (112) and processes the output signal. In one embodiment, the output circuit is implemented with a CMOS buffer and functions as a buffer with hysteresis. In another embodiment, the output circuit is implemented with an inverter and functions as an inverting buffer with hysteresis. In a third embodiment, the output circuit is implemented with a connection (i.e., signal conveyance) and functions as a non-inverting buffer with hysteresis.