Abstract: A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field.

Abstract: A coprocessor including a first multiplication circuit and a second multiplication circuit with a series input to receive n bits and a series output to give n+k bits. The coprocesser also includes addition and multiplexing circuits enabling the data elements produced by the multiplication circuits to be added up with one another and with other data elements encoded on n bits. The invention makes parallel use of the multiplication circuits to carry out modular or non-modular operations on pieces of binary data having n bits or more.

Abstract: A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first data element by a most significant word of the second data element. A test is performed to determine if the result of the division performed corresponds to a word of the final result sought. The first data element is modified by subtracting from it a data element produced by multiplying the second data element by the word of the final result sought that has been previously produced.

Abstract: The parameter J0 associated with the implementation of modular operations according to the Montgomery method is generated in an integrated circuit. J0 is encoded on Q*L bits such that J0=J0Q−1 . . . J00, wherein Q and L are integers. Loops are formed for the computation of the binary data elements J0j according to a known method, which is used for generating the sub-operands of L bits. A coprocessor is used for updating, by multiplication, of the value of a data element of Q*L bits of which the L least significant bits are used for the computation of the values of J0j.

Abstract: A modular arithmetic coprocessor designed to perform computations according to the Montgomery method includes a division circuit to perform integer divisions. The integer division circuit computes the division of a binary data element A encoded on n+n (bits by a binary data element B encoded on n bits, A, B, n, n' and n" being on-zero integers. For this function, the integer division circuit includes: a first n-bit register and a second n-bit register to contain the binary data element A and the result of the division, a third n-bit register to contain an intermediate result, a fourth n-bit register to contain the binary data element B, two subtraction circuits each having a first series input and a second series input and a series output, and a test circuit having an input and an output.

Abstract: The present invention relates to various methods and apparatus for obtaining a parameter J.sub.0 that is used in modular computations using the Montgomery method. The parameter J.sub.0 is defined by the formula (J.sub.0 *N.sub.0 +1)mod 2.sup.Bt =0, Bt being the working base in which the Montgomery method is carried out, and N.sub.0 being the Bt least significant bits of a modulo N used in the Montgomery method.

Abstract: Disclosed is a device including three registers, one input terminal to receive pieces of binary data to be stored in these registers, a multiplication circuit enabling the performance of a multiplication operation between two pieces of data stored in two of the registers, a first addition circuit enabling the performance of an addition operation between a piece of data stored in the second register and a piece of data produced by the multiplication circuit, a subtraction circuit placed between the second register and the addition circuit, a delay cell and a second addition circuit placed between the first addition circuit and the input of the second register, multiplexing circuitry making it possible to provide the contents of the second register or a permanent logic state to one input of one of the addition circuits, to connect another input of the addition circuit to an output of the multiplication circuit and to connect an output of the addition circuit to an input of the second register.

Abstract: Disclosed is an integrated circuit device enabling the computation of multiplication of A by B, especially a computation of the P.sub.field (A,B).sub.N type as defined in the Montgomery method, using a subdivision into words of Bt bits to carry out the different computations. This device is improved by the addition of a register of m * Bt bits containing the totality of the data element A. The invention also relates to a device for the implementation of a modular P.sub.field (A,B).sub.N operation according to the Montgomery method using the improved device presented by the invention.

Abstract: Disclosed is a method for producing a binary error correction parameter H=2.sup.(m1+m2)*k mod N by means of a coprocessor having registers with at most m*k bits, N being a binary data element encoded on m1 words of k bits, m1 being an integer greater than m, m, m2 and k being non-zero integers, the coprocessor including a first register, a register, a third register and a fourth register, a subtraction circuit and comparison circuitry. The disclosure thus proposes a circuit and a method specially suited to the required computation without excessively increasing the size of the coprocessor.

Abstract: Disclosed are a method and a circuit for computing an error correction parameter associated with the Montgomery method, using an exponentiation of 2.sup.m*k+1 mod N, by an exponent equal to k*m(, N being a modulo, encoded on k*m bits, associated with a modular operation using the Montgomery method, the Montgomery method automatically generating an error that it is necessary to correct if it is desired to perform a modular operation that is correct.

Abstract: A method for implementing modular reduction according to the Montgomery method, wherein a binary data element C is encoded on a number c of bits, grouped together in m' words of k bits, with m' and k as integers, m' being such that m'*k>c>(m'-1)*k, a non-zero binary data element N is encoded on a number n of bits. According to the disclosed method, to produce C mod N, steps are carried out for the production of a binary data element J0, associated with N, the production of at least one binary data element H having the form 2.sup.f(C,N), with f(C,N) as an integer representing the size of C and the parity of N, and the providing firstly of C, at the parallel input of a multiplication circuit having one serial input, one parallel input and one serial output, and secondly of H at the serial input of this same multiplication circuit.

Abstract: A method for producing a binary error correction parameter H=2.sup.2*m*k mod N with N being a binary data element, called a modulo, encoded on m words of k bits each. This method includes the following steps:1. loading of the modulo N into a first n-bit register with n=m*k and initialization of a second n-bit register at B(0)=02. production and storage of a data element B(1)=2*(B(0)-N) by bit-by-bit subtraction of B(0) and N, and left shift by one unit of the result, denoted R(0), of the bit-by-bit subtraction, and comparison of B(1) and N,3. production of a data element H.sub.int =2.sup.n+v mod N with v=(m*k)/2p, with p as an integer by the implementation of the following processing operation:for i as an integer from 1 to v,if B(i)<N then B(i+1)=2*B(i)-0),else B(i+1)=2*(B(i)-N),and bit-by-bit comparison of B(i+1) and N,4. production of the parameter H by the performance of p P.sub.field operations H.sub.int (j)=P(H.sub.int (j-1), H.sub.int (j-1))N, with j as an index ranging from 1 to p and H.sub.

Abstract: A method for the implementation of modular multiplication according to the Montgomery method, wherein a multiplicand A and a multiplier B are encoded respectively on a and b words of k bits, the most significant words of A and B being non-zero, a modulo N is encoded on m words of k bits, the modulo having (m-m') most significant words with k zero bits, with 0<m'<m. The method includes steps of multiplication in a multiplication circuit having a serial input to receive data elements encoded on at least m' words of k bits, a parallel input to receive encoded words of k bits, and a serial output, wherein, during the performance of the multiplication, a predetermined number p of words is given successively to the parallel input of the multiplication circuit, p being independent of m and greater than or equal to the number a.

Abstract: An electronic computation circuit comprises a multiplication operator with a serial input, a parallel input and a serial output, a first register connected by its output to the parallel input of the operator, a second register connected by its output to the serial input of the operator, a third register and a multiplexing circuit to selectively connect at least one data input terminal and the output of the operator to the inputs of the first, second and third registers, and to produce the output of the electronic multiplication circuit. Application to the operations of multiplication, squaring, exponentiation and modular inversion on a finite field denoted GF(2.sup.n).