Abstract: Embodiments described herein provide a system comprising a non-volatile storage memory, a controller, and a cognitive memory. The storage memory can store data. During operation, the controller programs a function for the system based on a configuration file. The function indicates one or more operations for the data stored in the storage memory. The cognitive memory can include a set of neuron memory cells, which can store a knowledge base for facilitating the function and execute a pattern matching operation between the data stored in the storage memory and the data stored in the set of neuron memory cells. The controller can then execute the one or more operations within the system based on an output of the pattern matching operation from the cognitive memory.

Abstract: The present invention is directed to an apparatus which can acquire, readout and perceive a scene based on the insertion, or embedding of photosensitive elements into or on a transparent or semi-transparent substrate such as glass or plastic. The substrate itself may act as the optical device which deflects the photons of an incident image into the photosensitive elements. A digital neural memory can be trained to recognize patterns in the incident photons. The photosensitive elements and digital neural memory elements may be arranged with light elements controlled in accordance with the patterns detected. In one application, intelligent lighting units provide light while monitoring surroundings and/or adjusting light according to such surroundings. In another application, intelligent displays display images and/or video while monitoring surroundings and/or adjusting the displayed images and/or video in accordance with such surroundings.

Abstract: The present invention is directed to an apparatus which can acquire, readout and perceive a scene based on the insertion, or embedding of photosensitive elements into or on a transparent or semi-transparent substrate such as glass or plastic. The substrate itself may act as the optical device which deflects the photons of an incident image into the photosensitive elements. A digital neural memory can be trained to recognize patterns in the incident photons. The photosensitive elements and digital neural memory elements may be arranged with light elements controlled in accordance with the patterns detected. In one application, intelligent lighting units provide light while monitoring surroundings and/or adjusting light according to such surroundings. In another application, intelligent displays display images and/or video while monitoring surroundings and/or adjusting the displayed images and/or video in accordance with such surroundings.

Abstract: The present invention is directed to an apparatus which can acquire, readout and perceive a scene based on the insertion, or embedding of photosensitive elements into or on a transparent or semi-transparent substrate such as glass or plastic. The substrate itself may act as the optical device which deflects the photons of an incident image into the photosensitive elements. A digital neural memory can be trained to recognize patterns in the incident photons. The photosensitive elements and digital neural memory elements may be arranged with light elements controlled in accordance with the patterns detected. In one application, intelligent lighting units provide light while monitoring surroundings and/or adjusting light according to such surroundings. In another application, intelligent displays display images and/or video while monitoring surroundings and/or adjusting the displayed images and/or video in accordance with such surroundings.

Abstract: The present invention is directed to an apparatus which can acquire, readout and perceive a scene based on the insertion, or embedding of photosensitive elements into or on a transparent or semi-transparent substrate such as glass or plastic. The substrate itself may act as the optical device which deflects the photons of an incident image into the photosensitive elements. A digital neural memory can be trained to recognize patterns in the incident photons. The photosensitive elements and digital neural memory elements may be arranged with light elements controlled in accordance with the patterns detected. In one application, intelligent lighting units provide light while monitoring surroundings and/or adjusting light according to such surroundings. In another application, intelligent displays display images and/or video while monitoring surroundings and/or adjusting the displayed images and/or video in accordance with such surroundings.

Abstract: An apparatus which can acquire, readout and perceive a scene based on the insertion, or etching of photosensitive elements into or on a transparent or semi-transparent substrate such as glass. The substrate itself acts as the optical device which deflects the photons incident to the reflected image into the photosensitive elements. Photosensitive elements are interconnected together by a transparent or opaque wiring. A digital neural memory can be trained to recognize specific scenery such as a human face, an incoming object, a surface defect, rain drops on a windshield and more. Other applications include image-perceptive car headlight and flat panel display detecting and identifying the viewer's behavior (gaze tracking, face recognition, facial expression recognition and more). Yet another application includes sliding doors perceiving the direction and speed of an individual coming towards that door.

Abstract: A sensor unit comprising a sensor, a neural processor and a communication device, wherein the sensor unit is adapted to perform pattern recognition by means of the neural processor and to transfer the result of the pattern recognition via the communication device.

Abstract: An apparatus which can acquire, readout and perceive a scene based on the insertion, or etching of photosensitive elements into or on a transparent or semi-transparent substrate such as glass. The substrate itself acts as the optical device which deflects the photons incident to the reflected image into the photosensitive elements. Photosensitive elements are interconnected together by a transparent or opaque wiring. A digital neural memory can be trained to recognize specific scenery such as a human face, an incoming object, a surface defect, rain drops on a windshield and more. Other applications include image-perceptive car headlight and flat panel display detecting and identifying the viewer's behavior (gaze tracking, face recognition, facial expression recognition and more). Yet another application includes sliding doors perceiving the direction and speed of an individual coming towards that door.

Abstract: An improved neuron and corresponding search operation for use in matching strings of characters from a character set or strings of pixels from an image is at least partly based on ZISC technology. Each neuron contains only one character in the string of characters to be searched or, equivalently, one pixel in the image to be searched. The neurons are lined up in order (unlike standard ZISC). The inventive system matches two strings of base-pairs, one of which is stored in the neurons, and the other of which is entered into the system input one character at a time and thereafter broadcast to all of the neurons. The inputs, outputs and contents of each neuron in the system include one stored base pair, a left_errors register; a right_errors register; a parallel sort bus; and a neuron number or location register. The operation may include the following steps: at the start of the operation, all left_errors and right_errors registers are reset to “0”.

Abstract: A neural network integrated circuit comprises many neuron circuits each with a distance resister that is compared in a competition for the closest-hit with all the other neurons. Such closest-hit comparison is conducted bit-by-bit over the many bit positions of a distance measure in binary format each time after the neurons fire. A single-wire AND-bus interconnects every neuron in a whole system. Each neuron drives the single-wire AND-bus with an open-collector buffer. All neurons press the single-wire AND-bus with their respective distance measures in successive cycles, starting with the most significant bit. For example, a fourteen-bit binary distance word requires fourteen comparison cycles. Any neuron that sees a “0” on the single-wire AND-bus when its own corresponding bit in its distance measure is a “1”, automatically drops from the competition. By the time the least significant bit cycle is run, a single closest distance will have been determined.

Abstract: A recognition system comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computers. Each field-programmable logic array device is configured to preprocess data from different respective media inputs and provide feature extraction vectors to the common vector-input port. Neural networks within the zero-instruction-set computer recognize the input patterns by comparing in parallel their vectors with those stored in each neural network cell. A variety of recognition jobs are made possible by changing the programming on-the-fly of the field-programmable logic array devices to suit each new job.

Abstract: In a neural network of N neuron circuits, having an engaged neuron's calculated p bit wide distance between an input vector and a prototype vector and stored in the weight memory thereof, an aggregate search/sort circuit (517) of N engaged neurons' search/sort circuits. The aggregate search/sort circuit determines the minimum distance among the calculated distances. Each search/sort circuit (502-1) has p elementary search/sort units connected in series to form a column, such that the aggregate circuit is a matrix of elementary search/sort units. The distance bit signals of the same bit rank are applied to search/sort units in each row. A feedback signal is generated by ORing in an OR gate (12.1) all local search/sort output signals from the elementary search/sort units of the same row. The search process is based on identifying zeroes in the distance bit signals, from the MSB's to the LSB's. As a zero is found in a row, all the columns with a one in that row are excluded from the subsequent row search.

Abstract: A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip.

Abstract: Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value.

Abstract: In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS).

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector.