Abstract: Adding a layer of abstraction to the generation of a runset for DRC rules, by defining a meta language hides from the user the language of a specific verification tool (also called “native language”). The meta language can be used directly by the user to express in a file (also called “meta runset”) the DRC rules to be used to create an input for the verification tool in the native language (also called simply “runset”). A runset generator uses DRC rules supplied by a user to generate a runset in a native language (that is identified by the user). The runset generator can use templates to generate a runset. Each template (also called “DRC template”) contains code (can be in source form or in object form) for implementation of a DRC rule or derived layer in the native language of a specific verification tool (such as HERCULES). Thus implementation of DRC rules is hidden from the novice user.

Abstract: A method automatically specifies a unique number of an error layer for each DRC rule in a runset. Therefore, all errors related to a given DRC rule are reported by a layout verification tool in the uniquely specified error layer. Furthermore, the method also automatically specifies a unique number of a filter layer that has the same extent as a quality assurance (QA) cell for testing the DRC rule. The filter layer is logically operated (e.g. ANDed) with the error layer to uniquely identify a failure related to the DRC rule (i.e. errors from all other QA cells are filtered out). The QA cells are generated automatically by use of a library of templates. During regression testing, the first time a DRC runset is run against a test design or QA cell library the results are manually verified and stored as “expected” results.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum ground rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguosuly arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing the chips density and performance versus hardware turn-around-time.