Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Abstract: The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit ICCMAX for the multi-core processor based on the number of active and constrained processor cores. Finally, the system communicates ICCMAX to a power-management mechanism within the multi-core processor. This enables the power-management mechanism to use ICCMAX to account for power saved by the constrained processor cores when the multi-core system is subsequently determining whether to change its operating frequency.

Abstract: The disclosed embodiments provide a system that operates a processor in a multi-core processor system. During operation, the system detects the creation of an asynchronous wakeup event for the processor. In response to detecting the creation of the asynchronous wakeup event, when the processor is subsequently placed into an idle state, the system configures the processor to resume operation at a reduced frequency that is a fraction of an operating frequency for the multi-core processor system, wherein the reduced frequency allows more power to be allocated to other processors in the multi-core processor system.

Abstract: The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit ICCMAX for the multi-core processor based on the number of active and constrained processor cores. Finally, the system communicates ICCMAX to a power-management mechanism within the multi-core processor. This enables the power-management mechanism to use ICCMAX to account for power saved by the constrained processor cores when the multi-core system is subsequently determining whether to change its operating frequency.

Abstract: The disclosed embodiments provide a system that operates a processor in a multi-core processor system. During operation, the system detects the creation of an asynchronous wakeup event for the processor. In response to detecting the creation of the asynchronous wakeup event, when the processor is subsequently placed into an idle state, the system configures the processor to resume operation at a reduced frequency that is a fraction of an operating frequency for the multi-core processor system, wherein the reduced frequency allows more power to be allocated to other processors in the multi-core processor system.