Abstract: Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device for selecting one of the MRAM cells, and a sense circuit for sourcing a sense current to measure the first and second resistance value; the sense circuit comprising a sample and hold circuit for performing said storing said first resistance value, and a differential amplifier circuit for performing said comparing the second resistance value to the stored first resistance value; wherein the controllable readout circuit further comprises a control circuit adapted to provide a pulse-shaped timing signal with a pulse duration controlling the duration of the first read cycle and the second read cycle. The controllable readout circuit allows for controlling the duration of the first and second read cycles after completion of the MRAM cell and readout circuit fabrication.

Abstract: Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device for selecting one of the MRAM cells, and a sense circuit for sourcing a sense current to measure the first and second resistance value; the sense circuit comprising a sample and hold circuit for performing said storing said first resistance value, and a differential amplifier circuit for performing said comparing the second resistance value to the stored first resistance value; wherein the controllable readout circuit further comprises a control circuit adapted to provide a pulse-shaped timing signal with a pulse duration controlling the duration of the first read cycle and the second read cycle. The controllable readout circuit allows for controlling the duration of the first and second read cycles after completion of the MRAM cell and readout circuit fabrication.

Abstract: A voltage regulating circuit has a clamp up circuit and a clamp down circuit operating in tandem. The clamp down circuit receives the unregulated voltage and an activation signal and in response thereto generates a first output signal at an output node in the event the unregulated voltage exceeds the first output signal. The clamp up circuit receives the unregulated voltage and an inverse of the activation signal and in response thereto generates a second output voltage at an output node in the event the unregulated voltage is below the second output voltage. The output node of the clamp down circuit is connected to the output node of the clamp up circuit. Thus, the output voltage is regulated to be between the first output voltage and the second output voltage.