Patents by Inventor Gwo-Long Lin
Gwo-Long Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160203693Abstract: A safety device for use in a bathroom includes a float and a detecting and controlling assembly. The float has a housing defining a receiving space. The detecting and controlling assembly is mounted in the receiving space. The detecting and controlling assembly includes an inclination detector, a processing unit, and a transmitting unit. The inclination detector and the transmitting unit are electrically connected to the processing unit. The inclination detector is adapted to detect a posture of the float and adapted to send a detection signal indicative of the posture of the float to the processing unit. The processing unit processes and analyzes the detection signal and sends out an emergency signal through the transmitting unit.Type: ApplicationFiled: February 25, 2015Publication date: July 14, 2016Inventors: Tsung-Cheng Wu, Tun-Hsueh Chan, Shih-Chiang Lin, Gwo-Long Lin, Ho-Hsuan Chang
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Patent number: 7480020Abstract: A transflective liquid crystal display and method of fabricating the same. The pixel region of the transflective comprises a thin film transistor, a transmissive electrode, and a reflective electrode, wherein the overlap of the reflective electrode and the transparent electrode composes a reflective region and the non-overlapping region of the reflective electrode and the transparent electrode form a transmissive region, and the transparent electrode and the source and the drain regions of the thin film transistor are formed of the same silicon layer.Type: GrantFiled: September 16, 2004Date of Patent: January 20, 2009Assignee: TPO Displays Corp.Inventors: Chi-Jain Wen, Dai-Liang Ting, Gwo-long Lin, Shyuan-Jeng Ho, I-Wei Wu
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Patent number: 7332379Abstract: A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.Type: GrantFiled: January 21, 2005Date of Patent: February 19, 2008Assignee: TPO Displays Corp.Inventors: Jr-Hong Chen, Gwo-Long Lin, Chih-Fang Chen
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Patent number: 7112458Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: GrantFiled: October 2, 2003Date of Patent: September 26, 2006Assignee: TPO Displays Corp.Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu
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Patent number: 7002652Abstract: A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.Type: GrantFiled: March 18, 2005Date of Patent: February 21, 2006Assignee: Toppoly Optoelectronics Corp.Inventors: Chi-Jain Wen, Dai-Liang Ting, Hsiao-Yi Lin, Gwo-Long Lin, I-Wei Wu
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Publication number: 20050186715Abstract: A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.Type: ApplicationFiled: January 24, 2005Publication date: August 25, 2005Inventors: Jr-Hong Chen, Gwo-Long Lin, Chih-Fang Chen
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Patent number: 6924874Abstract: The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. After that, a P-type source/drain is formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: GrantFiled: June 5, 2003Date of Patent: August 2, 2005Assignee: Toppoly Optoelectronics Corp.Inventors: Gwo-Long Lin, I-Min Lu, Chu-Jung Shih, Shyuan-Jeng Ho, I-Wei Wu
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Publication number: 20050146657Abstract: A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.Type: ApplicationFiled: March 18, 2005Publication date: July 7, 2005Inventors: Chi-Jain Wen, Dai-Liang Ting, Hsiao-Yi Lin, Gwo-Long Lin, I-Wei Wu
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Publication number: 20050072754Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: ApplicationFiled: October 2, 2003Publication date: April 7, 2005Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu
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Publication number: 20040239846Abstract: A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Inventors: Chi-Jain Wen, Dai-Liang Ting, Hsiao-Yi Lin, Gwo-Long Lin, I-Wei Wu
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Publication number: 20040096999Abstract: The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. After that, a P-type source/drain is formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: ApplicationFiled: June 5, 2003Publication date: May 20, 2004Inventors: Gwo-Long Lin, I-Min Lu, Chu-Jung Shih, Shyuan-Jeng Ho, I-Wei Wu
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Patent number: 6731352Abstract: A six mask-steps method for fabricating liquid crystal display is described. A driving area and a pixel area are defined by a first mask step. Gates on the driving/pixel area and upper electrodes of capacitors on the pixel area are defined by a second mask step. Then, using the gates and the upper electrodes as a mask, a source/drain, channel region and lower electrode are formed in the driving/pixel area by an ion-doping process. A second insulation layer is formed and covers the insulation substrate. A plurality of first openings is formed by the third mask step and the gate and the source/drain are exposed. A second conductive layer is formed and covers the second insulation layer and the first opening is filled. Then, the second conductive layer is patterned, and a source/drain line is formed and contacts electrically with the source/drain by the fourth mask step. A dielectric layer is formed and covers the second insulation layer and the second conductive layer; the dielectric layer has a planar surface.Type: GrantFiled: June 3, 2002Date of Patent: May 4, 2004Assignee: Toppoly Optoelectronics Corp.Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu, I-Wei Wu
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Publication number: 20030231268Abstract: A transmission-reflection switch plate made of polymer dispersed liquid crystal (PDLC) and/or related materials is used as an element of a transmission-reflection switch liquid crystal display.Type: ApplicationFiled: June 11, 2003Publication date: December 18, 2003Inventors: Jr-Hong Chen, Gwo-Long Lin, Chi-Jain Wen
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Publication number: 20030169394Abstract: A six mask-steps method for fabricating liquid crystal display is described. A driving area and a pixel area are defined by a first mask step. Gates on the driving/pixel area and upper electrodes of capacitors on the pixel area are defined by a second mask step. Then, using the gates and the upper electrodes as a mask, a source/drain, channel region and lower electrode are formed in the driving/pixel area by an ion-doping process. A second insulation layer is formed and covers the insulation substrate. A plurality of first openings is formed by the third mask step and the gate and the source/drain are exposed. A second conductive layer is formed and covers the second insulation layer and the first opening is filled. Then, the second conductive layer is patterned, and a source/drain line is formed and contacts electrically with the source/drain by the fourth mask step. A dielectric layer is formed and covers the second insulation layer and the second conductive layer; the dielectric layer has a planar surface.Type: ApplicationFiled: June 3, 2002Publication date: September 11, 2003Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu, I-Wei Wu
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Patent number: 6071762Abstract: A process for manufacturing a TFT without the use of ion implantation is described. Instead, heavily doped layers of amorphous silicon are used as diffusion sources. Two embodiments of the invention are described. In the first embodiment the gate pedestal is deposited first, followed by gate oxide and an amorphous layer of undoped silicon. This is followed by the layer of heavily doped amorphous silicon which is subjected to a relatively low energy laser scan which drives in a small amount of dopant and converts it to N-. After the N+ layer has been patterned and etched to form source and drain electrodes, a second, higher energy, laser scan is given. This brings the source and drain very close to, but not touching, the channel, resulting in an LDD type of structure. In the second embodiment a layer of intrinsic polysilicon is used for the channel. It is covered with a layer of gate oxide and a metallic gate pedestal.Type: GrantFiled: November 16, 1998Date of Patent: June 6, 2000Assignee: Industrial Technology Research InstituteInventors: Hong-Woei Wu, Yeong-E Chen, Gwo-Long Lin
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Patent number: 6063653Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned.Type: GrantFiled: July 7, 1998Date of Patent: May 16, 2000Assignee: Industrial Technology Research InstituteInventors: Kang-Cheng Lin, Gwo-Long Lin