Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A method and an apparatus are provided for image stabilization for the output of analog-to-digital converters (ADC) and for phase-locked loops (PLL). The digital coding at the output of ADCs and PLLs is filtered by this method and apparatus to eliminate the noise which has contaminated the coding. The noise sources are noise picked up by the cable, system board noise, ADC power and ground noise paths, and switching noise. The differences of energy level of sequential pixels in the ADC and PLL digital outputs used in image displays are used to decide if correction is required. The method of image noise filtering is compatible with programmable circuitry. This allows the method to be tuned for optimal image stabilization.

Abstract: The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream, which comprises N parallel signals divided into a first group of parallel signals and a second group of parallel signals, to be in accordance with a first sequence of N sampling pulses, and a sampling module sequentially samples each signal in the first group signals and the second group signals with the N sampling pulses in a second sequence and outputs a serial signal.

Abstract: The invention discloses a new architecture of multiphase delay-locked loop (DLL) with innovative 3-edge phase detector (3-edge PD), which compares the VCDL's first delay interval and the last delay interval to send an Up pulse or a Dn pulse to adjust the interval among those delay clock phases. The DLL may achieve both wide-range operation and multiple clock phase generation, and is also immune to multi-selection problem.

Abstract: A method and an apparatus are provided for image stabilization for the output of analog-to-digital converters (ADC) and for phase-locked loops (PLL). The digital coding at the output of ADCs and PLLs is filtered by this method and apparatus to eliminate the noise which has contaminated the coding. The noise sources are noise picked up by the cable, system board noise, ADC power and ground noise paths, and switching noise. The differences of energy level of sequential pixels in the ADC and PLL digital outputs used in image displays are used to decide if correction is required. The method of image noise filtering is compatible with programmable circuitry. This allows the method to be tuned for optimal image stabilization.

Abstract: This invention provides a method and apparatus for displaying an unscaled image frame on an LCD panel. The method and apparatus uses the same line buffers available to the digital signal processor DSP formerly used for scaling the displayed image up or down in size. No extra frame buffers are required by this invention since the frame rates of the source image and the LCD panel are the same. The image frame buffer is written to the LCD panel on every other panel vertical synchronization pulse. The vertical synchronization timing is shifted to the left or right in the time domain to center the image on the LCD panel.

Abstract: A method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading. A circuit is achieved comprising the above method.

Abstract: In this invention two compression circuits are combined to produce at a single output pass/fail condition for a plurality of memory addresses and a plurality of I/O. The output of an address compression circuit is connected to an I/O circuit. An I/O compression circuit is connected to several I/O circuits and the output of the I/O compression circuit controls a selected data output driver to provide a combined test result of the plurality of addresses and the plurality of I/O. The combination of the two compression circuits is made possible because the address data compression circuits and the I/O compression circuits use different truth tables.

Abstract: In this invention a double data rate (DDR) DRAM is read and written with data coherence. The data is in the form of a data burst either interleaved or sequential and of any length. The data is read from the DDR DRAM depending on whether the starting address is even or odd and taking into consideration CAS latency. Both edges of the clock are used to transfer data in and out of the DDR DRAM. To write data only the starting address of the data burst is used to maintain data coherence. Data coherence is assured by a write followed by a read of the same data to and from the same memory cell.

Abstract: An improved input buffer circuit of the type having a chain of FET inverter circuits has an FET connected in a feedback loop that functions like a Schmidt trigger and counteracts a hysteresis effect that causes variations in the delay of the inverter circuits and compensation for process variation. An FET is connected to conduct in its source-drain circuit between one of the power supply terminals and the interconnection node of two of the inverters in the chain. The gate of FET is connected to receive a signal from the output of one of the inverters. The hysteresis effect is characterized by different rising and falling paths at one knee of the transfer curve that describes the switching operation. The channel type of the FET and the polarity of the power supply terminal are selected to provide feedback during the transition where the knee occurs.

Abstract: An integrated circuit formed on a semiconductor substrate having multiple input/output signal paths such that the semiconductor substrate can be mounted to more than one package type. The integrated circuit formed on the semiconductor substrate has at least three pluralities of input output connector pads. The first plurality of input/output connector pads is placed on the semiconductor substrate and is attached to a first functional circuit of the integrated circuit. The second and third pluralities of input/output connector pads are placed on the semiconductor substrate and are attached to a second functional circuit of the integrated circuit. The third plurality of input/output connector pads is placed in an area separated from the first and second pluralities of input/output connector pads.

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Abstract: Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, in one cycle, two locations in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The circuits producing the two decoded outputs allow for sequential and interleaved mode, for data bursts of various lengths, and for addressing of redundant columns.

Abstract: A fast CMOS sense amplifier for semiconductor memories is disclosed. The memory sense amplifier configuration is comprised of differential pre-sense amplifier stage and a sense amplifier second stage. The pre-sense amplifier stage is composed of two sections with feedback between the sections which reduces the output swing by means of a clamping action, therefore improving output switching recovery time in response to differential input. The feedback between the sections is provided by cross connecting the sub outputs of each section to the gate of a clamping transistor at each section. The reduced recovery time produces reduced delay at the output which speeds up the operation of the sense amplifier. Additionally, the clamping devices have the effect of reducing the average DC current in the pre-sense amplifier.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks.