Patents by Inventor Gyo-Young Jin
Gyo-Young Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9349724Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.Type: GrantFiled: December 10, 2012Date of Patent: May 24, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon-bae Kim, Yong-chul Oh, Kuk-han Yoon, Kyu-pil Lee, Jong-ryul Jun, Chang-hyun Cho, Gyo-young Jin
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Patent number: 9276074Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.Type: GrantFiled: February 7, 2013Date of Patent: March 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jay-Bok Choi, Yoo-Sang Hwang, Ah-Young Kim, Ye-Ro Lee, Gyo-Young Jin, Hyeong-sun Hong
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Patent number: 8884340Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: GrantFiled: November 17, 2011Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8785998Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.Type: GrantFiled: December 21, 2012Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-woo Chung, Yong-chul Oh, Yoo-sang Hwang, Gyo-young Jin, Hyeong-sun Hong, Dae-ik Kim
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Publication number: 20130288472Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.Type: ApplicationFiled: February 7, 2013Publication date: October 31, 2013Inventors: Jay-Bok Choi, Yoo-Sang Hwang, Ah-Young Kim, Ye-Ro Lee, Gyo-Young Jin, Hyeong-sun Hong
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Patent number: 8492832Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.Type: GrantFiled: August 10, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-young Kim, Gyo-young Jin, Hyeong-sun Hong, Yoo-sang Hwang, Sung-kwan Choi, Hyun-woo Chung
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Publication number: 20130140265Abstract: A method of manufacturing a pattern structure, the method includes sequentially forming a mold layer and a mask layer on a substrate, patterning the mask layer to form a mask having a plurality of first and second holes located at vertices of hexagons that form a honeycomb structure, forming filling layer patterns in the first and second holes, removing the mask, forming a spacer on sidewalls of the filling layer patterns and the spacer has a plurality of third holes at centers of the hexagons, removing the filling layer patterns to form an etching mask including the spacer, and etching the mold layer using the etching mask to form the pattern structure having a plurality of openings located at the vertices and the centers of the hexagons.Type: ApplicationFiled: September 10, 2012Publication date: June 6, 2013Inventors: Cheon-Bae KIM, Kyu-Pil LEE, Chang-Hyun CHO, Gyo-Young JIN
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Publication number: 20130037882Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Inventors: Ji-young Kim, Gyo-young Jin, Hyeong-sun Hong, Yoo-sang Hwang, Sung-kwan Choi, Hyun-woo Chung
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Patent number: 8362536Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.Type: GrantFiled: October 14, 2010Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-woo Chung, Yong-chul Oh, Yoo-sang Hwang, Gyo-young Jin, Hyeong-sun Hong, Dae-ik Kim
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Publication number: 20120299090Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: ApplicationFiled: November 17, 2011Publication date: November 29, 2012Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8264022Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.Type: GrantFiled: October 28, 2009Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Gyo-young Jin, Hyeong-sun Hong, Makoto Yoshida, Bong-soo Kim
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Publication number: 20110284939Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.Type: ApplicationFiled: October 14, 2010Publication date: November 24, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-woo Chung, Yong-chul OH, Yoo-sang HWANG, Gyo-young JIN, Hyeong-sun HONG, Dae-ik KIM
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Patent number: 7833864Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.Type: GrantFiled: April 23, 2007Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chul Oh, Wook-Je Kim, Nak-Jin Son, Se-Myeong Jang, Gyo-Young Jin
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Publication number: 20100207241Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.Type: ApplicationFiled: October 28, 2009Publication date: August 19, 2010Inventors: Jae-man Yoon, Gyo-young Jin, Hyeong-sun Hong, Makoto Yoshida, Bong-soo Kim
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Patent number: 7737512Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.Type: GrantFiled: September 11, 2007Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Gyo-young Jin, Yong-chul Oh, Hyun-chang Kim
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Patent number: 7622778Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.Type: GrantFiled: May 12, 2006Date of Patent: November 24, 2009Assignee: Samsung Electronic Co., Ltd.Inventors: Sung-Sam Lee, Gyo-Young Jin, Yun-Gi Kim
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Patent number: 7501668Abstract: An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.Type: GrantFiled: October 18, 2006Date of Patent: March 10, 2009Assignee: Samung Electronics Co., Ltd.Inventors: Se-Myeong Jang, Yong-chul Oh, Gyo-young Jin
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Patent number: 7465988Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.Type: GrantFiled: October 12, 2007Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Sam Lee, Yong-Tae Kim, Mi-Youn Kim, Gyo-Young Jin, Dae-Won Ha, Yun-Gi Kim
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Publication number: 20080036016Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.Type: ApplicationFiled: October 12, 2007Publication date: February 14, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Sam LEE, Yong-Tae KIM, Mi-Youn KIM, Gyo-Young JIN, Dae-Won HA, Yun-Gi KIM
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Patent number: 7329927Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.Type: GrantFiled: June 24, 2005Date of Patent: February 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Gyo-young Jin, Yong-chul Oh, Hyun-chang Kim