Abstract: A semiconductor memory device includes a plurality of normal memory cells stacked over a substrate and coupled in series with each other, a plurality of selection transistors coupled in series, and one or more dummy memory cells coupled between the plurality of normal memory cells and the plurality of selection transistors, wherein the plurality of selection transistors includes first and second selection transistors, and the first selection transistor is adjacent to the dummy memory cells, and has a lower threshold voltage than the second selection transistor.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Abstract: A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Abstract: A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact area. A recess gate is formed in the gate area of the semiconductor substrate including the first groove. A first junction area is formed in the storage node contact area of the semiconductor substrate. A second junction area is formed in the bit line contact area of the semiconductor substrate under the second groove.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Abstract: The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

Abstract: The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

Abstract: A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact area. A recess gate is formed in the gate area of the semiconductor substrate including the first groove. A first junction area is formed in the storage node contact area of the semiconductor substrate. A second junction area is formed in the bit line contact area of the semiconductor substrate under the second groove.

Abstract: The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention isolates a semiconductor substrate by an oxide layer with only a source, a drain and a channel region necessary for driving a transistor being left. Thus, it can obviate the current components due to parasitic factors to improve the punch-through characteristic.

Abstract: A method for fabricating a semiconductor memory device using a silicon-on-insulator device, including forming a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

Abstract: A semiconductor memory device, comprising: a semiconductor layer including a cell region and a peripheral region; a first insulating layer formed over a lower surface of the semiconductor layer and having first and second contact holes exposing the cell region and the peripheral region, respectively; first isolation layers formed in the semiconductor layer of the cell region; second isolation layers formed in the semiconductor layer of the peripheral region to define a device formation region in the peripheral region; a pair of trench layers formed to a define a device formation region in the semiconductor layer of the cell region and formed in the semiconductor layer between the first isolation layers to be spaced from the lower surface of the semiconductor layer; a cell transistor formed in the device formation region between the trench layers in the cell region, the cell transistor including a first gate having a first gate oxide formed over an upper surface of the semiconductor layer in the device formati

Abstract: A semiconductor memory device using a silicon-on-insulator device, including a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

Abstract: Disclosed is a method for fabricating CMOS device using a SOI substrate, and more particularly the method for fabricating CMOS device capable of improving mobility of electron and hole.