Patents by Inventor Gyung-Su Cho

Gyung-Su Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8137363
    Abstract: An electrical dermabrasion device (10) for exfoliating a foot includes a hollow main body (12); an abrasion unit (32, 42) connected to the main body (12), for exfoliating the foot; and a driving unit (14, 16, 18) incorporated in a hollow portion of the main body (12), for rotating the abrasion unit (32, 42).
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: March 20, 2012
    Inventor: Gyung Su Cho
  • Patent number: 7163884
    Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 7144308
    Abstract: Apparatus for chemical mechanical polishing are disclosed. A disclosed apparatus includes a polishing station having a polishing pad, a gas supplier to generate pressurized gas to press a wafer toward the polishing pad, and a polishing head assembly including a planar member having a plurality of fine holes in communication with the gas supplier and a membrane to press the wafer toward the polishing pad due to the pressurized gas received through the plurality of fine holes, wherein the plurality of fine holes are arranged to rotate at different radii of rotation when the planar member rotates.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: December 5, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Gyung-Su Cho
  • Publication number: 20060057947
    Abstract: Apparatus for chemical mechanical polishing are disclosed. A disclosed apparatus includes a polishing station having a polishing pad, a gas supplier to generate pressurized gas to press a wafer toward the polishing pad, and a polishing head assembly including a planar member having a plurality of fine holes in communication with the gas supplier and a membrane to press the wafer toward the polishing pad due to the pressurized gas received through the plurality of fine holes, wherein the plurality of fine holes are arranged to rotate at different radii of rotation when the planar member rotates.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 16, 2006
    Inventor: Gyung-Su Cho
  • Publication number: 20050136645
    Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 23, 2005
    Inventor: Gyung-Su Cho
  • Publication number: 20040099949
    Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.
    Type: Application
    Filed: October 1, 2003
    Publication date: May 27, 2004
    Inventor: Gyung-Su Cho
  • Patent number: 6028000
    Abstract: The present invention discloses a forming method for metal wiring in a semiconductor device with different sized contact holes. The metal wiring in a semiconductor device according to the present invention is formed by the following processes. First, a semiconductor substrate on which an insulation film having a plurality of different sized contact holes is formed is provided. A barrier metal layer is then formed on the substrate and a first tungsten film is formed on entire surface of the barrier metal layer thick enough to fill relatively smaller contact hole among the different sized contact holes. Next, the first tungsten film and the barrier metal layer are removed to expose the top surface of the insulation film. A second tungsten film is formed selectively on the contact holes thick enough to completely fill relatively larger contact hole among the different sized contact holes and the surface of the substrate is then planarized.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: February 22, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 5937326
    Abstract: A method for making a semiconductor device having a via hole, includes the steps of depositing a second metal layer onto a first insulating layer formed on a semiconductor substrate where a first metal layer is formed on its lower surface, and forming a first photoresist layer. The second metal layer is then etched, using the first photoresist layer as a first etching mask, to form a metal line. Thereafter, the first photoresist layer is removed and a second photoresist layer is formed over the metal line. The metal line is etched, using the second photoresist layer as a second etching mask, to make the metal line protrude. The inventive method further includes a step for depositing a second insulating layer onto the metal line, forming a third photoresist layer on the second insulating layer, and etching the second insulating layer, using the third photoresist layer as a third etching mask, for the formation of a via hole on the metal line.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: August 10, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 5804509
    Abstract: Method of forming intermetallic insulating layers in semiconductor devices are disclosed, which not only have superior adhesion and homogeneous step coverage but also prevent the generation of voids due to the penetration of moisture. According to the method, metal interconnects are, first formed on the semiconductor substrate. Thereafter, a first insulating layer is formed to a thickness capable of sufficiently filling the spaces between the metal interconnects by reacting Tetraethylorthosilicate(TEOS) gas of a predetermined flow rate with O.sub.3 gas of a predetermined density in a CVD furnace. Next, a second insulating layer of a predetermined thickness is formed on the first insulating layer using the same furnace but by changing only the flow rate of TEOS.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: September 8, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 5713717
    Abstract: A multi-substrate feeder used in a semiconductor device manufacturing system is disclosed. The multi-substrate feeder precisely feeds a plurality of substrates to desired positions at the same time. The multi-substrate feeder has an arm support plate having a cylindrical rotor in the center thereof. A plurality of substrate feeding arms are movably placed on the arm support plate to feed a plurality of substrates at the same time. Each substrate feeding arm is mounted to the edge of the rotor at one end thereof and used for holding a substrate on the other end thereof. The feeder also has arm guide means for guiding the movement of the substrate feeding arms on the arm support plate to guide the substrate feeding direction of the feeder.
    Type: Grant
    Filed: June 22, 1995
    Date of Patent: February 3, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung Su Cho
  • Patent number: 5670427
    Abstract: A method for forming metal contacts in an integrated circuit, comprises the steps of: forming a first insulating layer on a silicon substrate; forming and patterning a first metal layer on the first insulating layer; forming and patterning a photoresist layer on the first insulating layer and the first metal pattern such that portions of the first insulating layer and first metal pattern are partially exposed; etching the exposed portion of the first metal pattern using the photoresist pattern to form a fine metal pattern; removing the photoresist pattern; depositing a second insulating layer on the overall surface of the structure; removing the second insulating layer to a depth until the fine metal pattern is exposed; coating a third photoresist layer on a surface of the second insulating layer and a surface of the fine metal pattern; patterning the third photoresist layer such that the surface of the fine metal pattern and portions of the surface of the second insulating layer adjacent to and on both sides
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: September 23, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 5648298
    Abstract: A method of forming a contact of a semiconductor device is disclosed. An insulating film and a metal oxide film having different etch rates are deposited on a semiconductor substrate. A photoresist pattern is formed so that the width thereof is the minimum line width which can be obtained using a conventional exposure equipment. When the insulating film and metal oxide film are etched using the photoresist pattern, since the etch rates are different from one another, a contact hole is formed than that is a finer than that at a conventional contact hole. Accordingly, a fine contact can be manufactured without purchasing additional equipment, and can be applied for semiconductor devices with higher integration.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: July 15, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gyung-Su Cho