Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Abstract: A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: In a storage card, a first module exposes a set of registers including a first register to the host through a configuration space of a host interface, and the first register is written when the host submits a command of an I/O request to the host memory. A second module fetches the command from the host memory when the first register is written. A third module detects a location of the host memory based on a host memory address of request information in response to signaling of the second module, and performs a transfer of target data between the host memory and a memory controller. A fourth module writes a completion event to the host memory through the configuration space in response to service completion of the I/O request in the third module, and informs the host about I/O completion by writing an interrupt.

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change memory, and a request queue stores the write request. A scheduler returns a completion on the write request to the CPU when a predetermined write time has elapsed. The predetermined write time is shorter than a write latency time that is taken to complete the data write to a memory cell of the memory device in response to the write request.

Abstract: In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change memory, and a request queue stores the write request. A scheduler returns a completion on the write request to the CPU when a predetermined write time has elapsed. The predetermined write time is shorter than a write latency time that is taken to complete the data write to a memory cell of the memory device in response to the write request.

Abstract: A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.