Abstract: A system and method for storing a plurality of trace records in a memory and searching, by a hardware processor, the plurality of trace records for specific trace data from the trace records, the searching including feeding the trace records back into a hardware real time event processor that collected the trace records.

Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: A system and method for storing a plurality of trace records in a memory and searching, by a hardware processor, the plurality of trace records for specific trace data from the trace records, the searching including feeding the trace records back into a hardware real time event processor that collected the trace records.

Abstract: A method includes capturing a plurality of trace capture records and storing the plurality of trace capture records in a trace acquisition protocol record. The trace acquisition protocol record further storing a single timestamp record and a plurality of flag records. A number of flag records corresponds to a number of trace capture records stored in the trace acquisition protocol record.

Abstract: Described is a protocol controller that supports calls to a packet subroutine which includes a packet processing engine programmed to retrieve packets from a packet memory and to interpret the packets, a working chain pointer module of the packet processing engine programmed to generate a packet memory address for each packet and a return address register of the working chain pointer module, adapted to store a return packet address. Upon processing a call packet, the packet processor engine instructs the working chain pointer module to save a next packet address of a normal packet flow in the return address register, and instructs the working chain pointer module to generate the packet address to execute the packet routine.