Abstract: An error detection and correction apparatus and method in a memory system for performing single symbol error correction and at least double symbol error detection of data errors and single symbol error detection and at least double symbol error detection of addressing errors using a modified Reed Solomon code. A first of three parity symbols in a codeword is used to determine the value of a single symbol error, if any, over a memory word comprising data symbols and its corresponding address comprising address symbols. A second parity symbol is used to locate a single symbol error, and a third parity symbol is used to detect at least two errors in the data and address symbols. The three parity symbols are used to generate syndromes which determine if there is an error and what corrective action to take.

Abstract: Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic on such integrated circuit. Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller. In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions.

Abstract: Apparatus and method for providing programmable fault insertion circuitry in a large scale integrated (LSI) circuit device thereby eliminating the need for external switches or relays to create faults. A fault parameter word is stored in a register and the outputs of the register are decoded to select the fault condition to be inserted by an interfacing circuit to the logic being tested. Test vectors and the fault parameter word are generated by a controller coupled to the integrated circuit and a test response from the integrated circuit is examined by the controller.

Abstract: A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that individual bytes of each word are aligned in columns. Each column of bytes is addressable independently of the other byte columns via adders. A most significant bit portion of a memory location address is fed into a first input of column adders and the output of a first decoder circuit is fed into a second input of the adders for address incrementing within one memory cycle. A second decoder circuit generates a separate read or write enable line to each column of bytes. Both decoders are controlled by a least significant bit portion of the memory address and reference word byte size codes. A bi-directional multiplexer rearranges the order of the bytes so they appear in the proper order at the memory interface.