Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.

Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

Abstract: A semiconductor device includes: a control signal generation unit configured to generate a second control signal having a cycle shorter than a first control signal in response to a clock signal and the first control signal; a cyclic redundancy check (CRC) control unit configured to perform a control to receive first and second data groups in response to the second control signal, and to output the first and second data groups with a time lag; and a CRC operation unit configured to perform a cyclic redundancy check on each of the first and second data groups sequentially output through the CRC control unit.

Abstract: A semiconductor device includes: an inversion circuit suitable for inverting a first data clock in response to an inversion signal; a first phase detection unit suitable for comparing a phase of the first data clock transferred from the inversion circuit with a phase of a system clock and generating a first detection result; a second phase detection unit suitable for comparing a phase of a second data clock with the phase of the system clock and generating a second detection result; an inversion signal generation unit suitable for generating the inversion signal that is enabled when the first detection result and the second detection result are different from each other; a first transferring unit suitable for transferring the first detection result; and a second transferring unit suitable for transferring the second detection result.

Abstract: A semiconductor device includes: a control signal generation unit configured to generate a second control signal having a cycle shorter than a first control signal in response to a clock signal and the first control signal; a cyclic redundancy check (CRC) control unit configured to perform a control to receive first and second data groups in response to the second control signal, and to output the first and second data groups with a time lag; and a CRC operation unit configured to perform a cyclic redundancy check on each of the first and second data groups sequentially output through the CRC control unit.

Abstract: A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

Abstract: A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

Abstract: A semiconductor memory apparatus may include a cyclic redundancy check (CRC) circuit block electrically coupled with a first pad, and configured to generate internal CRC information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external CRC information received from outside the semiconductor memory apparatus with the internal CRC information, and generate a read training result signal.

Abstract: A data output circuit may include a first node, which receives a first strobe signal, a second node, which receives a second strobe signal, an input control unit that is coupled to the first and second nodes, and receives the first strobe signal generated from a single strobe signal transmitted through a first path of a semiconductor memory apparatus and the second strobe signal generated from the single strobe signal transmitted from a second path of the semiconductor memory apparatus in response to a read command, generates a first input control signal based on the first strobe signal and the second strobe signal, and generates a second input control signal based on the second strobe signal.

Abstract: The technology may include: a first error detection operation unit configured to perform a serial error detection operation on a data signal which is inputted in sequence through each of multiple input/output pads, and to generate multiple pieces of preliminary information; and a second error detection operation unit configured to perform a parallel error detection operation on the multiple pieces of preliminary information, and to generate an error detection code.

Abstract: A semiconductor memory apparatus may include a cyclic redundancy check (CRC) circuit block electrically coupled with a first pad, and configured to generate internal CRC information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external CRC information received from outside the semiconductor memory apparatus with the internal CRC information, and generate a read training result signal.

Abstract: The technology may include: a first error detection operation unit configured to perform a serial error detection operation on a data signal which is inputted in sequence through each of multiple input/output pads, and to generate multiple pieces of preliminary information; and a second error detection operation unit configured to perform a parallel error detection operation on the multiple pieces of preliminary information, and to generate an error detection code.