Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.

Abstract: A memory device includes a first memory having first hardware properties, a second memory having second hardware properties different from the first hardware properties, and a controller configured to receive a signal, representing the first or second hardware properties, with a command to select the first memory or the second memory based on the received signal. The controller controls the selected first or second memory such that an operation according to the command is performed on the selected first or second memory.

Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.

Abstract: A memory expanding device includes an input and output part coupleable to an external optical interface, a controller coupled to the input and output part through a first internal optical interface, a main memory module coupled to the controller through a second internal optical interface, and a sub-memory module coupled to the controller through a first internal electrical interface.

Abstract: A subsystem comprises a master and a plurality of slaves. The master comprises a clock generator for generating a first clock signal and a second clock signal which have different frequency each other. When command and address signals are received from the master, the plurality of slaves transmits the corresponding data signals to the master. Here, the first clock signal is used to require command and address signals to the corresponding slave, and the second clock signal is used to transmit data signals into the corresponding slave, thereby preserving the improved signal integrity to a command and address buses and simplifying circuit blocks, communication methods and system configuration.

Abstract: The present invention generally relates to a memory device. More particularly, the present invention relates to a memory system for receiving chip selecting signals and a plurality of control signals from a memory controller. The memory system comprises: a chip selecting determiner for deciding whether the chip selecting signals are enabled; a main operation command table for defining a predetermined operation corresponding to combination of the control signals when the chip selecting signals are enabled; a preliminary operation command table for defining a predetermined operation corresponding to combination of the control signals when the chip selecting signals are disabled; and a logic circuit unit for decoding the combination of the control signals into a predetermined operation, based on the main operation command table or the preliminary operation command table according to enable conditions of the chip selecting signals from the chip selecting determiner.

Abstract: A column redundancy circuit for a semiconductor memory device, includes a plurality of DQ region units each including a memory cell array unit having cells sharing a local data bus and a global data bus, a column decoder unit for generating a column decoding signal for selecting one of the cells, a write driver unit for driving input data to the global data bus, and a read sense amp unit for amplifying input data, and transmitting the data to a global I/O line; and a repair region unit being provided at one side of the DQ regions, and consisting of a repair cell array unit having repair cells sharing the local data bus and the global data bus, N column decoder units for generating a column decoding signal for selecting one of the repair cells, N write driver units for driving input data to the repair global data bus, N read sense amp units for amplifying input data, and transmitting the data to the global I/O line, N DQ selection fuse box units for programming information of the DQ region unit having a defect

Abstract: A column redundancy circuit for a semiconductor memory device, includes a plurality of DQ region units each including a memory cell array unit having cells sharing a local data bus and a global data bus, a column decoder unit for generating a column decoding signal for selecting one of the cells, a write driver unit for driving input data to the global data bus, and a read sense amp unit for amplifying input data, and transmitting the data to a global I/O line; and a repair region unit being provided at one side of the DQ regions, and consisting of a repair cell array unit having repair cells sharing the local data bus and the global data bus, N column decoder units for generating a column decoding signal for selecting one of the repair cells, N write driver units for driving input data to the repair global data bus, N read sense amp units for amplifying input data, and transmitting the data to the global I/O line, N DQ selection fuse box units for programming information of the DQ region unit having a defect

Abstract: Disclosed is a semiconductor memory device comprising a precharging unit between bit lines within a memory cell region and bit lines within a sense amplifier region, respectively. When performing a column operation on the bit lines within the sense amplifier region upon consecutive read operations, the bit lines within the memory cell region are precharged and a wordline is disabled, and thus the memory cell region comes to the ready to enable a new wordline. Accordingly, the timing of row and column operations can be reduced, thereby reducing a data access time and realizing a high speed operation.