Abstract: An optical receiver includes a soft-decision deciding unit (7) for deciding an electric received signal according to a plurality of decision levels to output a multivalued decision signal, a demultiplexing unit (5) for serial-to-parallel converting the multivalued decision signal to output a multivalued parallel signal, a soft-decision error correction decoding unit (8) for correcting the multivalued parallel signal based on reliability information to output an error-corrected parallel received signal and decision results indicating the decision of the electric received signal according to the plurality of decision levels, a probability density distribution estimation unit (9) for estimating probability density distributions based on distributions of the decision results, and a decision level control unit (10) for controlling the plurality of decision levels based on the probability density distributions, thereby improving the transmission quality.

Abstract: A decoding method of a product code calculates a kth soft output value of each of r C1 codewords [Ct] (t=1, 2, . . . , r) detected at a codeword generating step. Beginning from t=1, if a kth value of a C1 codeword [Ct] is zero, a first variable, with a predetermined initial value, is compared with the likelihood of the codeword. The first variable is substituted with the sum of a greater one of the first variable and the likelihood and a correction value of the difference between them. If the kth value is nonzero, then the second variable is updated in the same manner. The update of the first and second variables is carried out with incrementing t from one to r, and the kth soft output value is calculated from the difference between the first and second variables updated.

Abstract: A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

Abstract: An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46?ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.

Abstract: In a conventional turbo-code decoding apparatus, there is a need for calculating a state transition probability for MAP decoding of convolutional codes composing turbo codes in an error correcting decoder and a channel state needs to be measured based on soft decision information to calculate the probability, by which an arithmetic operation amount is enormously increased. Turbo-code error correction decoding is performed by executing operations in a branch metric based forward path metric calculation step of calculating a forward path metric based on a branch metric with calculating the branch metric for a transition to an adjacent time point and a soft decision information calculation step of calculating N bits of soft decision information based on the branch metric, the forward path metric, and a backward path metric with calculating the backward path metric based on the branch metric.

Abstract: A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.

Abstract: In a conventional turbo error-correcting decoder, the soft-decision information is corrected by using an average value (A) and a variance value (&sgr;2) of reliability of received bits. From the reliability-corrected soft-decision information, the hard-decision information is obtained. This process of calculation is complex, giving rise to a problem of reduced processing speed and complicated circuit. To deal with this problem, an average value of reliability of received information bits is determined and then a ratio between the average value and the soft-decision information is also determined. This ratio is converted by the conversion table into the reliability-corrected soft-decision information, from which the hard-decision information is obtained.

Abstract: An RS encoding circuit encodes for error correction bits for information symbols in which information bits are assigned to low-order bits and dummy bits are assigned to high-order bits so as to generate bits for parity symbols such that the number of bits per information symbol is equal to the number of bits per parity symbol. A symbol conversion circuit subjects high-order bits for parity symbols to symbol conversion.

Abstract: A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

Abstract: A decoding method of a product code calculates a kth soft output value of each of r C1 codewords [Ct] (t=1, 2, . . . , r) detected at a codeword generating step. Beginning from t=1, if a kth value of a C1 codeword [Ct] is zero, then compare the first variable, the initial value of which is predetermined, with the likelihood of the codeword, and substitute into the first variable the sum of a greater one of the first variable and the likelihood and a correction value of the difference between them. If the kth value is nonzero, then the second variable is updated in the same manner. The update of the first and second variables is carried out with incrementing t one by one from one to r, and the kth soft output value is calculated from the difference between the first and second variables updated.

Abstract: A demodulation method includes: a coset estimation step for estimating a low-order information bit based on a log-likelihood ratio of the low-order information bit and estimating a parity bit based on a log-likelihood ratio of the parity bit, so as to estimate a coset based on the low-order information bit and the parity bit; and a high-order information bit estimation step for estimating a transmitted signal point based on the coset so as to estimate a high-order information bit based on the transmitted signal point.

Abstract: An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.

Abstract: In the conventional digital radio communications, ½ or more of a channel capacity has been used for error control. Thus, error resistance is high, and a digital compressed moving picture can be transmitted within a short time in the case of high-speed transmission. However, when large-capacity information, such as image data, is transmitted in low bit data transmission, e.g., a digital MCA system, transmission takes a long time even when an error is small on a transmission path. Conversely, a reduction in redundancy shortens transmission time, but reduces error resistance. Consequently, in the case of digital compressed image data, it was impossible to reproduce an image with respect to a 1-bit error. A method is disclosed for protecting data by correcting a plurality of errors.

Abstract: A decoding unit includes a first decoder and a second decoder. The decoding unit further includes an input/output interface for inputting received code sequences, and channel value memories for storing the received codes sequences. Placing prior values at their initial value of zero, the first decoder decodes a first block, and the second decoder decodes a second block of the received code sequences in parallel. Among the decoded results, that is, posterior values and external values, the external values are stored in an external value memory. In the next decoding, the external values are read as prior values. The decoding process is repeated by a predetermined number of times, and posterior values of the final decoded result is output from the input/output interface as the decoded result. The decoding unit can reduce the time required for decoding because of the parallel decoding of the blocks.

Abstract: An error correcting method decides the impossibility of error correction on the basis of only syndrome values and estimates a double error from only an operation expression B and, in a particular case where the impossibility of error correction cannot be decided based only on the syndrome values, decides the impossibility of error correction from the values of operation expressions, too.

Abstract: An error correcting decoding apparatus of an extended RS code capable of solving a problem of a conventional method in that Euclidean algorithm or Berlekamp-Massey algorithms must be performed twice in the worst case because of complicated algorithm, and this results in a delay of decoding. The present apparatus generates a syndrome from a received word, estimates the number of errors having occurred in the received word, computes error-locator polynomials and error-value polynomials while changing the initial values and ending condition of the Euclidean algorithm computation in accordance with the number of errors estimated, computes error locations and error values by performing Chien's search on these polynomials, and carries out the error correction on the basis of the error locations and error values. This makes it possible to achieve decoding by performing the Euclidean algorithm computation only once.

Abstract: In an error-correcting decoder, in which an input digital signal including reliability information is decoded by using a Viterbi algorithm as a first decoding process and a final decoded result is obtained by block-code decoding as a second decoding process, a flag signal is added to a location where a value of reliability of path metric determined by the Viterbi algorithm is lower than a threshold, as an original flagged location. A flag signal adding unit continuously adds flag signals to locations, from the original flagged location to locations preceding the originally flagged location, after back tracing. The flagged locations are then regarded as erasure locations in the block-code decoding process.