Patents by Inventor HADAS OSHINSKY

HADAS OSHINSKY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11853595
    Abstract: A stream set classification process may be implemented to classify streams opened by a host device on a data storage device. The data storage device may internally classify the streams into different stream classifications using a set of performance metrics. Stream classifications that cause the data storage device to show the greatest gains when compared with a set of baseline performance metrics for the data storage device and/or when compared with other stream classifications, may be selected by the data storage device and/or the host device for subsequent write operations.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Matar Krizhak, Stella Achtenberg, Hadas Oshinsky
  • Patent number: 11842069
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman
  • Patent number: 11809736
    Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman, Karin Inbar
  • Patent number: 11809747
    Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Oren Ben Hayun, Rotem Sela, Alex Lemberg
  • Publication number: 20230333772
    Abstract: A stream set classification process may be implemented to classify streams opened by a host device on a data storage device. The data storage device may internally classify the streams into different stream classifications using a set of performance metrics. Stream classifications that cause the data storage device to show the greatest gains when compared with a set of baseline performance metrics for the data storage device and/or when compared with other stream classifications, may be selected by the data storage device and/or the host device for subsequent write operations.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Einav Zilberstein, Matar Krizhak, Stella Achtenberg, Hadas Oshinsky
  • Publication number: 20230229347
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.
    Type: Application
    Filed: February 4, 2022
    Publication date: July 20, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman
  • Publication number: 20230222055
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Einav ZILBERSTEIN, Hadas OSHINSKY, Yuliy IZRAILOV
  • Publication number: 20230195353
    Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman, Karin Inbar
  • Publication number: 20230195376
    Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Oren Ben Hayun, Rotem Sela, Alex Lemberg
  • Patent number: 11520695
    Abstract: A storage system determines whether its memory is fragmented (e.g., based on a host read pattern that indicates that a sequential file is being read, but the number of data sense operations required to perform this read indicates that file is stored non-sequentially in the memory). If the storage system determines that its memory is fragmented, the storage system can perform a defragmentation operation on the memory. This defragmentation operation can be done invisibly to the host (i.e., without receiving any hint or instruction from the host to perform the defragmentation operation).
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky
  • Publication number: 20220283934
    Abstract: A storage system determines whether its memory is fragmented (e.g., based on a host read pattern that indicates that a sequential file is being read, but the number of data sense operations required to perform this read indicates that file is stored non-sequentially in the memory). If the storage system determines that its memory is fragmented, the storage system can perform a defragmentation operation on the memory. This defragmentation operation can be done invisibly to the host (i.e., without receiving any hint or instruction from the host to perform the defragmentation operation).
    Type: Application
    Filed: March 29, 2021
    Publication date: September 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky
  • Patent number: 11199997
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 10901620
    Abstract: A storage system and method for thin provisioning are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to provide a logical exported capacity of the memory to a host, wherein the logical exported capacity is greater than an actual storage capacity of the memory; receive a command from the host to write data to a logical address; determine whether there is available actual storage capacity in the memory to write the data; and write the data to a physical address in memory that corresponds to the logical address only if it is determined that there is available actual storage capacity in the memory to write the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Michael Zaidman, Rotem Sela, Hadas Oshinsky
  • Patent number: 10712972
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 14, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Publication number: 20200192606
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 18, 2020
    Inventors: Amir SHAHARABANY, Hadas OSHINSKY
  • Patent number: 10564891
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 10534709
    Abstract: A data storage device includes a write cache, a non-volatile memory and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a plurality of flush commands, write all data from the write cache to the non-volatile memory while executing fewer than all of the plurality of flush commands.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hadas Oshinsky, Rotem Sela, Amir Shaharabany
  • Patent number: 10481816
    Abstract: Apparatus, systems, methods, and computer program products for providing dynamically assignable data latches are disclosed. A non-volatile memory die includes a non-volatile memory medium. A plurality of sets of data latches of a non-volatile memory die are configured to facilitate transmission of data to and from a non-volatile memory medium, and each of the sets of data latches are associated with a different identifier. An on-die controller is in communication with a sets of data latches. An on-die controller is configured to receive a first command for a first memory operation comprising a selected identifier. An on-die controller is configured to execute a first memory operation on a non-volatile memory medium using a set of data latches of a plurality of sets of data latches, and the set of data latches is associated with a selected identifier.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 19, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark Shlick, Hadas Oshinsky, Amir Shaharabany, Yoav Markus
  • Patent number: 10430328
    Abstract: Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 1, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Rotem Sela, Miki Sapir, Amir Shaharabany, Hadas Oshinsky, Rafi Abraham, Elad Baram
  • Patent number: 10372341
    Abstract: A controller addresses portions of non-volatile memory via a memory interface using physical addresses and addresses portions of host data via the host interface using logical addresses. The controller maintains logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses. The controller is configured to move data from a source logical address to a destination logical address by updating logical to physical mappings and physical address to logical mappings without instructing the non-volatile memory to move the data between physical locations. In one embodiment, this process is used to implement a command to move or defragment data.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hadas Oshinsky, Rotem Sela, Amir Shaharabany