Abstract: Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

Abstract: Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

Abstract: A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

Abstract: A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.

Abstract: A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

Abstract: A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.

Abstract: A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

Abstract: A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage supply noise, temperature fluctuations and uncorrelated crosstalk, the receiver data may shift and/or the eye may collapse if the CDR is not turned ON to take care of these modulations. To address such disadvantages, it is proposed to generate a CDR profile that can specify optimum CDR ON and OFF time so that link stability may be maintained while saving power.

Abstract: A code converter is provided. The code converter includes a plurality of serial shift registers arranged to convert an input to a thermometer output. The code converter further includes a plurality of clock control circuits each configured to provide a clock to a corresponding one of the shift registers. A method of generating a signal in thermometer code is provided. The method includes enabling a subset of a plurality of shift registers and converting an input to a thermometer output by the plurality of shift registers. Another code converter is further provided. The code converter includes means for converting an input to a thermometer output. The means for converting includes a plurality of shift registers. The code converter further includes means for enabling a subset of the shift registers.