Abstract: Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.

Abstract: Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.

Abstract: A semiconductor device in which a silica aerogel layer having a very low dielectric constant is used as an insulating layer such that parasitic capacitance between a gate electrode and a source electrode in a field effect transistor having a T-shaped gate electrode, and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, source and drain electrodes, which are formed on the semiconductor substrate to make ohmic contact with the semiconductor substrate, a T-shaped gate electrode, which is formed between the source and drain electrodes on the semiconductor substrate, and an insulating layer including a silica aerogel layer, the silica aerogel layer being interposed between the gate electrode and the source and drain electrodes.

Abstract: A semiconductor device in which a silica aerogel layer having a very low dielectric constant is used as an insulating layer such that parasitic capacitance between a gate electrode and a source electrode in a field effect transistor having a T-shaped gate electrode, and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, source and drain electrodes, which are formed on the semiconductor substrate to make ohmic contact with the semiconductor substrate, a T-shaped gate electrode, which is formed between the source and drain electrodes on the semiconductor substrate, and an insulating layer including a silica aerogel layer, the silica aerogel layer being interposed between the gate electrode and the source and drain electrodes.

Abstract: A pseudomorphic high electron mobility transistor (PHEMT) power device formed on a double planar doped epitaxial substrate and capable of operating with a single voltage source and a method for manufacturing the PHEMT power device are provided. The PHEMT power device includes: an epitaxial substrate including a GaAs buffer layer, an AlGaAs/GaAs superlattice layer, an updoped AlGaAs layer, a first doped silicon layer, a first spacer, an InGaAs electron transit layer, a second spacer, a second doped silicon layer having a different doping concentration from the first doped silicon layer, a lightly doped AlGaAs layer, and an undoped GaAs cap layer stacked sequentially on a semi-insulating GaAs substrate; a source electrode and a drain electrode formed on and in ohmic contact with the undoped GaAs cap layer; and a gate electrode formed on the lightly doped AlGaAs layer to extend through the undoped GaAs cap layer.

Abstract: A pseudomorphic high electron mobility transistor (PHEMT) power device formed on a double planar doped epitaxial substrate and capable of operating with a single voltage source and a method for manufacturing the PHEMT power device are provided. The PHEMT power device includes: an epitaxial substrate including a GaAs buffer layer, an AlGaAs/GaAs superlattice layer, an updoped AlGaAs layer, a first doped silicon layer, a first spacer, an InGaAs electron transit layer, a second spacer, a second doped silicon layer having a different doping concentration from the first doped silicon layer, a lightly doped AlGaAs layer, and an undoped GaAs cap layer stacked sequentially on a semi-insulating GaAs substrate, a source electrode and a drain electrode formed on and in ohmic contact with the undoped GaAs cap layer; and a gate electrode formed on the lightly doped AlGaAs layer to extend through the undoped GaAs cap layer.