Abstract: In one embodiment an electronic device comprises at least one processor, at least one PCI express link, a virtual channel/sub-link flow control module, and a memory module communicatively connected to the one or more processors and comprising logic instructions which, when executed on the one or more processors configure the one or more processors to determine, in an electrical device, whether a virtual channel/sub-link is inactive, and in response to a determination that at least one virtual channel/sub-link is inactive, reallocate queue space from the at least one inactive channel to at least one active channel.

Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

Abstract: In one embodiment an electronic device comprises at least one processor, at least one PCI express link, a virtual channel/sub-link flow control module, and a memory module communicatively connected to the one or more processors and comprising logic instructions which, when executed on the one or more processors configure the one or more processors to determine, in an electrical device, whether a virtual channel/sub-link is inactive, and in response to a determination that at least one virtual channel/sub-link is inactive, reallocate queue space from the at least one inactive channel to at least one active channel.

Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

Abstract: In at least some embodiments of the invention, a system may comprise a plurality of electronic devices adapted to send and receive data, wherein each electronic device uses any one of a plurality of communication protocols. The system may also comprise a switch comprising a plurality of ports, each port is adapted to couple to an electronic device, wherein each port is configurable for use according to the protocol used by the electronic device coupled thereto.

Abstract: A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The memory controller may store such data into a prefetch buffer.

Abstract: Performance improved transaction identification queue structures and techniques for implementing such structures. Specifically, a read queue structure and a dropped queue structure are provided in a host/data controller. Once the read queue structure is filled with read requests, any read requests corresponding to transactions that can be completed without retrieving data from main memory may be moved to the dropped queue structure. The dropped queue structure may provide substitute entrypoints for storage of subsequent read requests.

Abstract: A multinodal multiprocessor computer system and method is provided in which a first processor can acquire exclusive access to a first memory location in a shared memory, and at the same time a second processor can access to a second memory location of the shared memory that is located in the same node or in any other node of the computer system. Memory controllers in each node of the computer system control access to the shared memory. A switch coupled to each of the memory controllers maintains a lock register, which is shadowed by each of the memory controllers, for controlling access to the first memory location.

Abstract: Apparatus and methods that are directed to an electronic device that may include control logic and a plurality of ports configurable by the control logic as determined by a programmable register to operate as a single communication link to a single device or as a plurality of independent communication links to a plurality of devices.

Abstract: A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The memory controller may store such data into a prefetch buffer.

Abstract: Performance improved transaction identification queue structures and techniques for implementing such structures. Specifically, a read queue structure and a dropped queue structure are provided in a host/data controller. Once the read queue structure is filled with read requests, any read requests corresponding to transactions that can be completed without retrieving data from main memory may be moved to the dropped queue structure. The dropped queue structure may provide substitute entrypoints for storage of subsequent read requests.

Abstract: A multinodal multiprocessor computer system and method is provided in which a first processor can acquire exclusive access to a first memory location in a shared memory, and at the same time a second processor can access to a second memory location of the shared memory that is located in the same node or in any other node of the computer system. Memory controllers in each node of the computer system control access to the shared memory. A switch coupled to each of the memory controllers maintains a lock register, which is shadowed by each of the memory controllers, for controlling access to the first memory location.

Abstract: A computer network is equipped to facilitate increased bandwidth for a large number of network data communications among a number of network devices. A software switch is configured to provide a number of ports through which data packets may be transmitted from a transmitting device to a receiving device. Each port is activated utilizing a software thread function. For each port, a port and socket is assigned and activated for communications between various identified transmitter/receiver network device pairings. Subsequent transmission between previously identified transmitter/receiver device pairings receive the same port and socket assignments as previously determined. Generation of a second layer of software thread functions are provided associated with the socket thread function to utilize the send and receive functionality of each bi-directional port.