Patents by Inventor Hai Ming
Hai Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979808Abstract: A radio communication method and a terminal device are provided. In a D2D communications system, the terminal device may determine an RAT for transmitting data, so as to ensure reliable transmission of the data. The method is applied to device-to-device communication through a PC5 carrier comprising obtaining configuration information indicates a correspondence between identifier of services and at least one Radio Access Technology (RAT) that comprises a plurality of access layer parameters, determining, at least one access layer parameter for transmitting a first service according to the configuration information, wherein the first service belongs to the at least one service, and transmitting the first service by using the at least one access layer parameter.Type: GrantFiled: June 22, 2020Date of Patent: May 7, 2024Assignee: Guangdong OPPO Mobile Telecommunications Corp., Ltd.Inventors: Hai Tang, Huei-Ming Lin
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Publication number: 20240145571Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.Type: ApplicationFiled: January 5, 2023Publication date: May 2, 2024Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11963468Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
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Publication number: 20240113225Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wu-Wei Tsai, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240113222Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.Type: ApplicationFiled: January 3, 2023Publication date: April 4, 2024Inventors: Yan-Yi Chen, Wu-Wei Tsai, Yu-Ming Hsiang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240054011Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry performs data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 12, 2023Publication date: February 15, 2024Applicant: Intel CorporationInventors: Rajesh M. Sankaran, Philip R. Lantz, Narayan Ranganathan, Saurabh Gayen, Sanjay Kumar, Nikhil Rao, Dhananjay A. Joshi, Hai Ming Khor, Utkarsh Y. Kakaiya
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Publication number: 20240039437Abstract: A method of controlling a sensorless motor (32). The method contains the steps of determining a current speed of the motor (32); selectively using a first method, a second method, or a third method to determine a position of a rotor of the motor (32), depending on the current speed of the motor (32); and transmitting a drive signal to the motor (32) based on the determined position of the rotor. A sensorless motor assembly is also disclosed. According to the method, multiple rotor position detection methods are provided to the sensorless motor (32) which cover a full speed range of the motor (32).Type: ApplicationFiled: February 25, 2021Publication date: February 1, 2024Inventors: Hai Ming LUO, Hai Bo MA, Yong Sheng GAO
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Patent number: 11722131Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.Type: GrantFiled: November 23, 2020Date of Patent: August 8, 2023Assignee: Wenzhou UniversityInventors: Pengjun Wang, Hai Ming Zhang, Yue Jun Zhang, Gang Li, Bo Chen
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Publication number: 20230141188Abstract: The subject invention pertains to an evaporation strategy combined with low-molecular-weight polyacrylic acid (LPAA) to generate an antibacterial dental enamel-like structure. Polystyrene (PS) plates can be used as a removable substrate for the continuous growth of fluorapatite (FAP). The FAP-LPAA composition can be used to kill microorganisms. The LPAA contained dental enamel-like FAP provides an alternative to prevent secondary caries if a carious cavity is filled with shaped dental enamel-like FAP-LPAA.Type: ApplicationFiled: November 9, 2022Publication date: May 11, 2023Inventors: Hai Ming WONG, Quan Li LI, Le ZHANG
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Patent number: 11616037Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: GrantFiled: May 11, 2022Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20230085939Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.Type: ApplicationFiled: November 23, 2020Publication date: March 23, 2023Applicant: Wenzhou UniversityInventors: Pengjun WANG, Hai Ming ZHANG, Yue Jun ZHANG, Gang LI, Bo CHEN
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Publication number: 20230032236Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 27, 2022Publication date: February 2, 2023Applicant: Intel CorporationInventors: Rajesh M. Sankaran, Philip R. Lantz, Narayan Ranganathan, Saurabh Gayen, Sanjay Kumar, Nikhil Rao, Dhananjay A. Joshi, Hai Ming Khor, Utkarsh Y. Kakaiya
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Publication number: 20220359436Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Publication number: 20220352109Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.Type: ApplicationFiled: August 29, 2021Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Nien-Fang Wu, Hai-Ming Chen, Yu-Min Liang, Jiun-Yi Wu
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Publication number: 20220270994Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: ApplicationFiled: May 11, 2022Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 11424199Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: GrantFiled: November 11, 2019Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Patent number: 11355461Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: GrantFiled: June 29, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20220116932Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Applicant: WIRELESS FUTURE TECHNOLOGIES INC.Inventors: Erlin Zeng, Hai Ming Wang, Xiangguang Che, Chun Yan Gao, Peng Chen, Jing Han, Bernhard Raaf
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Patent number: 11212782Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.Type: GrantFiled: January 23, 2020Date of Patent: December 28, 2021Assignee: WIRELESS FUTURE TECHNOLOGIES, INC.Inventors: Erlin Zeng, Hai Ming Wang, Xiangguang Che, Chun Yan Gao, Peng Chen, Jing Han, Bernhard Raaf
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Patent number: 11127644Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.Type: GrantFiled: September 13, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Hai-Ming Chen, Yu-Min Liang, Jung Wei Cheng, Chien-Hsun Lee