Abstract: Example implementations relate to combined backup power. For example, a system for combined backup power can include a combined backup power supply (CBPS) coupled to a node and a plurality of loads supported by the node. The CBPS can include an uninterruptible power supply (UPS) and a backup power supply coupled to the UPS to act as redundancy for the UPS.

Abstract: Examples herein disclose receiving a communication indicating a number of loads supported by multiple nodes and determining an amount of power available at a backup power source. Based on the determination of the amount of power, the examples disclose delivering power to the multiple nodes from the backup power source.

Abstract: Examples herein disclose determining when a battery module is below a full charge and selecting a subset of loads based on a prioritization among multiple loads. The selected subset of loads is to receive power from the battery module. The examples herein deliver power to the selected subset of loads.

Abstract: A system in accordance with an example includes a first load and a second load. The first load includes a first power supply connected to a first uninterruptible power supply (UPS). The second load includes a second power supply connected to a second UPS, where the first UPS is connected to the second UPS. The first power supply is to deliver power to the first load and to the second load when power to the second load is disabled, and the second power supply is to deliver power to the second load and to the first load when power to the first load is disabled.

Abstract: Described are examples of back-up power apparatuses and systems including such back-up power apparatuses. An example may include a battery module, and a back-up power control module to determine a back-up power demand of a host device and selectively enable an output of power from the battery module to the host device if the battery module has a power capacity greater than the back-up power demand.

Abstract: Examples disclose an uninterruptible power supply comprising an integrated circuit. The integrated circuit comprises a charger to charge a battery and an inverter to deliver output power from the battery to a load. The integrated circuit further comprises an active filter to reduce input current to the uninterruptible power supply by compensating a power factor corresponding to input power.

Abstract: Examples disclose a system with a first power module with a first switch to deliver power to a load by connecting the first switch. Further, the examples provide the system with a second power module with a second switch to deliver the power to the load by connecting the second switch, the power to the load from either the first power module or the second power module. Additionally, the examples also disclose a battery to provide voltage to either the first power module or the second power module to enable the delivery of the power to the load by alternating between the first switch in the first module and the second switch in the second power module.

Abstract: A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.

Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.

Abstract: A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.

Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.

Abstract: A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.