Abstract: A pan-tilt-zoom device includes a housing, a carrier, an image sensor, and a shape memory alloy (SMA) motor. An accommodating cavity is formed in the housing, and a first opening in communication with the accommodating cavity is provided on the housing. The carrier is located in the accommodating cavity, the carrier has a lens mounting hole, and an opening at one end of the lens mounting hole faces the first opening. The image sensor is located in the accommodating cavity and is disposed on a side that is of the carrier and that is away from the first opening, and a photosensitive surface of the image sensor faces an opening at the other end of the lens mounting hole. The SMA motor is configured to drive the carrier to tilt in the accommodating cavity along with the image sensor in any direction around, to implement optical image stabilization.

Abstract: A BGP route identification method and apparatus are provided. A network device obtains a BGP route. The BGP route includes an autonomous system path attribute AS_PATH attribute, the AS_PATH attribute includes a first autonomous system number AS number, an AS number corresponding to an autonomous system that the network device is located in or manages is a second AS number, and the first AS number is equal to the second AS number. The network device determines, based on the first AS number and the second AS number, whether the BGP route is abnormal.

Abstract: A compound of formula (I) or an optical isomer thereof, and pharmaceutically acceptable salts, prodrugs, aquo-complexes or non-aqueous-solvent complexes thereof are provided. Experiments prove that, compared with a control compound MGL-3196, the compound of formula (I), which is obtained through specific substitution sites and specific substitution types, is higher in agonist activity to THR-beta and significantly improved in selectivity on THR-beta/THR-alpha. The compound can be used in preparing THR-beta agonist and drugs for treating adaption diseases (including dyslipidemia, hypercholesteremia, non-alcoholic steatohepatitis and non-alcoholic fatty liver disease) applicable to the THR-beta agonist.

Abstract: An automatic yarn feeding system is provided. The system comprises a yarn feeding track which is arranged on the twisting machine in a length direction of the twisting machine and provided with a yarn feeding manipulator walking along the yarn feeding track; and a supply zone which is arranged on one side of the yarn feeding track and used to buffer base yarns. The yarn feeding manipulator is used to convey the base yarns from the supply zone to a yarn feeding creel of each spindle position. The yarn feeding track is located in the middle of the top of the twisting machine. The supply zone is provided with a structure for buffering a plurality of base yarns, and is located on one side of an end of the yarn feeding track on the top of a control cabinet.

Abstract: The present invention proposes an in-situ freezing machining method for an integrated thin-walled array structure. In the method, the area among cups is cut off first; then, the outer walls of a cup array are machined; and finally, water filling and freezing are carried out, and in-situ freezing machining of the inner walls of the cup array is carried out. Then, hoisting and turning over are carried out, and the area among cavities is cut off; then, the outer walls of a cavity array are machined; and finally, water filling and freezing are carried out, and in-situ freezing machining of the inner walls of the cavity array is carried out. The method realizes in-situ freezing clamping of workpieces, avoids error accumulation caused by repeated installation of a fixture, and can refrigerate efficiently, suppress ambient and cutting thermal interference, and ensure the stability of freezing fixture.

Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.

Abstract: The present invention provides a method and a system for train periodic message scheduling based on a multi-objective evolutionary algorithm, relating to the field of information and communications technology, mainly including: acquiring an MVB periodic message table; binary encoding the MVB periodic message table and initializing it randomly, to generate an iterative population; performing crossover and mutation operations on the individuals of the iterative population using a genetic algorithm, to update the iterative population; constructing an MVB periodic scheduling table that meets scheduling needs and minimizes the macro cycle according to a multi-objective algorithm and the updated iterative population; scheduling train periodic messages according to the MVB periodic scheduling table, thereby meeting the real-time requirement of periodic data transmission in actual scheduling scenarios.

Abstract: In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to convert a first value to a second value based on a mapping relationship between a read gray code and a program gray code, perform a program operation to program the second value into a memory cell as a state based on the read gray code, and perform a read operation to read out the state from the memory cell based on the read gray code to be the first value.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: Disclosed are an array substrate, a liquid crystal display panel, and a control method. The array substrate (1) comprises a plurality of connecting wire assemblies (20) and a driver (30), each connecting wire assembly (20) comprises a wiring group (22) and an acquisition module (21), the acquisition module (21) is used to detect the electrical parameters of the wiring group (22) and feed them back to the driver (30). The present disclosure can adjust the input voltage according to the impedance of the wiring group (20), so that the driving voltage of each data line or each scanning line is the same and the display uniformity can be improved.

Abstract: A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a target memory cell of the memory cells into one of x intermediate levels based on all pages of N pages of the piece of N-bits data to be stored in the target memory cell, where x is an integer smaller than 2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the target memory cell into one of the 2N levels based on all pages of the N pages of the piece of N-bits data to be stored in the target memory cell.

Abstract: A preparation method of a low-cost passivated contact full-back electrode solar cell includes: performing alkali polishing on a Si wafer; performing RCA cleaning and HF cleaning; growing a tunnel SiOx film layer, an in-situ doped amorphous Si film layer, and a texturing mask layer on the back of the Si wafer; performing annealing activation on the amorphous Si film layer to form a polycrystalline Si film layer; etching the texturing mask layer; performing double-sided texturing on the Si wafer; performing HF cleaning to remove the texturing mask layer; depositing an AlOx film on the front and back of the Si wafer; depositing a SiNx passivation film on the front and back of the Si wafer; ablating a part of the AlOx film and a part of the SiNx passivation film on the back of the Si wafer; and performing screen-printing and sintering on the back of the Si wafer.

Abstract: A novel method for synthesizing deuterated amides and deuterated sulfonamides includes the following steps: (1) adding a compound M, DMAP, R3—X to a solvent to obtain a compound N after a reaction is complete; and (2) adding the compound N, R4—NH—R5, or a salt and base thereof to a solvent, and purifying after a reaction is complete to obtain a compound I.

Abstract: The present disclosure relates to a method and a device for recognizing hand gestures in real-time. A shape is given as an input in a form of a binary image. The shape contour is partitioned into radial and angular spaces by an Angular Radial Bin distribution including multiple concentric circles and angular space partitions in a way that multiple angular radial sections are created denoted Angular Radial Bins. The ARB distribution is angle tilted through its centre of mass multiple times and the same procedure is repeated in order to capture a shape descriptor from different angle perspectives. A shape descriptor is calculated for each of an angle tilted instance of the ARB distribution belonging to a sequence of angle tilted instances of the ARB distribution.