Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.

Abstract: Disclosed in the present application are a thin film transistor, a manufacturing method therefor, a display panel, and a display device. The thin film transistor includes a base substrate, and a metal conductive material, a first silicon-based intermediate layer and a first gate insulating layer sequentially located on the base substrate, where the first silicon-based intermediate layer is bonded to the metal conductive material and the first gate insulating layer by means of chemical bonds.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate comprises a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode being corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrode and the gate line, the gate insulating layer having a first via hole and a second via hole, the first via hole exposing the gate electrode, the second via hole exposing the gate line, a conductive connection layer and a polysilicon semiconductor layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the gate line with the gate electrode.

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.

Abstract: Embodiments of the disclosure provide a display substrate and a method for manufacturing the same. The display substrate includes: a base substrate; a thin film transistor including a source-drain metal layer and a first insulating layer; a second insulating layer; a color resist layer; and a third insulating layer. The third insulating layer comprises a first via hole that sequentially penetrates the third insulating layer, the color resist layer and the second insulating layer and thus extends from the third insulating layer to the source-drain metal layer. A sidewall of the first via hole comprises a first portion formed of a material of the second insulating layer, a second portion formed of a material of the color resist layer, and a third portion formed of a material of the third insulating layer, the second portion is between the first portion and the third portion.

Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.

Abstract: The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.

Abstract: The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.

Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate comprises a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode being corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrode and the gate line, the gate insulating layer having a first via hole and a second via hole, the first via hole exposing the gate electrode, the second via hole exposing the gate line, a conductive connection layer and a polysilicon semiconductor layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the gate line with the gate electrode.

Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.

Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.

Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.

Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.

Abstract: The present disclosure provides a manufacturing method of thin film transistor, a thin film transistor and a display substrate. The manufacturing method comprises sequentially forming a polysilicon pattern layer and a protective pattern layer on a substrate; etching the protective pattern layer with a first etching gas, so as to obtain a protective pattern; simultaneously etching the protective pattern and the polysilicon pattern layer with a second etching gas by using the protective pattern as a mask, so as to obtain a polysilicon pattern and a residual protective pattern, the protective pattern being etched with the second etching gas at a rate no less than that for etching the polysilicon pattern layer; and forming an amorphous silicon pattern, which is in contact with etched sides of the polysilicon pattern, exposes a part of the residual protective pattern, and forms an active layer together with the polysilicon pattern.

Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.