Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

Abstract: A guide plate for spine surgery incl odes a guide plate body. The guide plate body includes a medial surface matching the back surface of surgical segment centrum. The guide plate body is provided with a guide hole. The outer surface of guide block is conical, the guide plate body is provided with a drill hole corresponding to the guide block. The drill hole matches the outer surface of front end of guide block, the guide block is embedded in the drill hole.

Abstract: Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

Abstract: Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

Abstract: A liquid-crystal-on-silicon device generates an image for projection onto a screen. The device includes a front plane, a back plane including a pixel driving circuit, and a wall that forms a chamber between the front and back planes for holding liquid crystal. Electrodes protrude into the chamber from the front plane, back plane, or both, in a predetermined pattern. The electrodes may be shaped as pillars and may serve as anodes or cathodes or both. When a voltage is applied to the electrodes, the liquid crystal assumes different polarization states at different pixel sites to form an image which may be projected onto a screen.

Abstract: A liquid-crystal-on-silicon device generates an image for projection onto a screen. The device includes a front plane, a back plane including a pixel driving circuit, and a wall that forms a chamber between the front and back planes for holding liquid crystal. Electrodes protrude into the chamber from the front plane, back plane, or both, in a predetermined pattern. The electrodes may be shaped as pillars and may serve as anodes or cathodes or both. When a voltage is applied to the electrodes, the liquid crystal assumes different polarization states at different pixel sites to form an image which may be projected onto a screen.

Abstract: Embodiments of the invention provide a digital micro-display device including two symmetric banks of pixel array blocks, which form the active display area, memory control and pixel look up tables (LUTs), and supporting data-paths and memory structures. Power straps are automatically generated. Initial power and ground pin locations are determined for each block. Locations are relocated based upon the actual placement and orientation of the placed blocks from which a set of strapping wires (lengths and widths) may be determined.

Abstract: Embodiments of the invention provide a driver device for delivery of pixel values in a digitally encoded (PWM) fashion to a LCOS imager, such as a 2-megal pixel imager. In particular, modulated pixel values may be delivered to a LCOS imager. Driver device functions as a high definition imager driver and transmits a PWM pixel stream through interface to imager. Pixel input stream may be received by low I/O buffer which may be implemented as a voltage differential signaling (LVDS) I/O buffer. The data may then be processed at input block, and restored into frame buffer banks. Through pixel lookup tables, the frame data gets transformed into a PWM pulse train and shifted off driver device onto an imager. Frame buffer to signal generator interface may include multiplexers for reordering bits before signal generation.