Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

Abstract: An audio encoding and decoding method and a related apparatus are provided. The audio encoding method includes: determining a channel combination scheme for a current frame; when the channel combination scheme for the current frame is different from a channel combination scheme for a previous frame, performing segmented time-domain downmix processing on left and right channel signals in the current frame based on the channel combination scheme for the current frame and the channel combination scheme for the previous frame, to obtain a primary channel signal and a secondary channel signal in the current frame; and encoding the obtained primary channel signal and secondary channel signal in the current frame.

Abstract: A stereo signal encoding method includes: obtaining a residual signal encoding parameter of a current frame of a stereo signal based on downmixed signal energy and residual signal energy of each of M sub-bands of the current frame, where the residual signal encoding parameter indicates whether to encode residual signals of the M sub-bands; determining whether to encode the residual signals based on the residual signal encoding parameter; and encoding the residual signals when it is determined that the residual signals need to be encoded.

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Abstract: A method and an apparatus for calculating a downmixed signal and a residual signal are provided. According to the method, if a first target frame (a current frame or a previous frame of the current frame) is a switching frame, a to-be-encoded downmixed signal and a to-be-encoded residual signal of the subband corresponding to the preset frequency band in the current frame is calculated based on a switch fade-in/fade-out factor of a second target frame, an initial downmixed signal and an initial residual signal of the preset frequency band.

Abstract: This application discloses a downmixed signal calculation method and apparatus. The method includes: when a current frame or a previous frame of the current frame of a stereo signal is not a switching frame and a residual signal in the current frame or the previous frame does not need to be encoded, obtaining a second downmixed signal in the current frame and a downmix compensation factor of the current frame, correcting the second downmixed signal in the current frame based on the downmix compensation factor of the current frame, to obtain the first downmixed signal in the current frame and determining the first downmixed signal in the current frame as a downmixed signal in the current frame in a preset frequency band.

Abstract: A non-transitory computer-readable medium is provided. The non-transitory computer-readable medium having computer instructions stored therein, which when executed by one or more processors, cause the one or more processors to perform operations. The operations comprise: determining a channel combination scheme for a current frame, where the determined channel combination scheme for the current frame is one of a plurality of channel combination schemes; and determining a coding mode of the current frame based on a channel combination scheme for a previous frame and the channel combination scheme for the current frame, where the coding mode of the current frame is one of a plurality of coding modes.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Abstract: Embodiments of the present disclosure provide a method and apparatus for capturing video, an electronic device and a computer-readable storage medium. The method includes: receiving a video capture trigger operation from a user via a video playing interface for an original video; superimposing a video capture window on the video playing interface, in response to the video capture trigger operation; receiving a video capture operation from the user via the video playing interface: and capture a user video in response to the video capture operation, and displaying the user video via the video capture window. According to the embodiments of the present disclosure, a user only needs to perform operations related to capturing a user video on the video playing interface, thereby implementing a function of combining video, and the operation process is simple and fast. The user video can represent the user's feelings, comments, or viewing reactions to the original video.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-channel replacement metal gate device and methods of manufacture. The structure includes: a fully depleted semiconductor on insulator substrate; a plurality of fin structures over the fully depleted semiconductor on insulator substrate; and a metal gate structure spanning over the plurality of fin structures and the fully depleted semiconductor on insulator substrate.

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Abstract: The present invention discloses a unit commitment method considering security region of wind turbine generators with frequency response control, and the main steps are: 1) determining security region of wind turbine generators when provides frequency response; 2) based on the security region of the wind turbine generators when provides frequency response, establishing a unit commitment model considering security region of wind turbine generators; and 3) calculating the unit commitment model considering the security region of the wind turbine generators by using mixed-integer linear programming method, and obtaining the operation result of the unit commitment considering the security region of the wind turbine generators with frequency response control. The present invention can be widely used in the setting of frequency response parameters of wind turbine generators dispatched in the prior art and the start-stop and output plans of synchronous generator.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.