Patents by Inventor Haiyan Gong
Haiyan Gong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672461Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.Type: GrantFiled: January 22, 2014Date of Patent: June 2, 2020Assignee: Nvidia CorporationInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Patent number: 9842631Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.Type: GrantFiled: December 14, 2012Date of Patent: December 12, 2017Assignee: NVIDIA CORPORATIONInventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu, Haiyan Gong
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Patent number: 9542992Abstract: A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.Type: GrantFiled: April 18, 2013Date of Patent: January 10, 2017Assignee: NVIDIA CorporationInventors: Hwong-Kwo Lin, Ge Yang, Fei Song, Xi Zhang, Haiyan Gong
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Publication number: 20160336054Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Stephen FELIX, Hwong-Kwo LIN, Spencer GOLD, Jing GUO, Andreas GOTTERBA, Jason GOLBUS, Karthik NATARAJAN, Jun YANG, Zhenye JIANG, Ge YANG, Lei WANG, Yong LI, Hua CHEN, Haiyan GONG, Beibei REN, Eric VOELKEL
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Patent number: 9484115Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: GrantFiled: May 13, 2015Date of Patent: November 1, 2016Assignee: NVIDIA CorporationInventors: Stephen Felix, Hwong-Kwo Lin, Spencer Gold, Jing Guo, Andreas Gotterba, Jason Golbus, Karthik Natarajan, Jun Yang, Zhenye Jiang, Ge Yang, Lei Wang, Yong Li, Hua Chen, Haiyan Gong, Beibei Ren, Eric Voelkel
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Patent number: 9355710Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.Type: GrantFiled: January 23, 2014Date of Patent: May 31, 2016Assignee: NVIDIA CORPORATIONInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Publication number: 20150206577Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Applicant: Nvidia CorporationInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Publication number: 20150206576Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: Nvidia CorporationInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Patent number: 9071240Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.Type: GrantFiled: September 25, 2012Date of Patent: June 30, 2015Assignee: Nvidia CorporationInventors: Hank Lin, Ge Yang, Xi Zhang, Jiani Yu, Haiyan Gong
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Publication number: 20140313817Abstract: A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.Type: ApplicationFiled: April 18, 2013Publication date: October 23, 2014Applicant: NVIDIA CORPORATIONInventors: Hwong-Kwo LIN, Ge YANG, Fei SONG, Xi ZHANG, Haiyan GONG
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Publication number: 20140169108Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: NVIDIA CORPORATIONInventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu, Haiyan Gong
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Publication number: 20140084984Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Applicant: NVIDIA CORPORATIONInventors: Hank Lin, Ge Yang, Xi Zhang, Jiani Yu, Haiyan Gong