Abstract: The present invention relates to a carbide tool cleaning and coating production line and a method, including a cleaning device including a support frame, a cleaning mechanism and a drying mechanism are sequentially disposed under the support frame connected to a moving mechanism, the moving mechanism is connected to a lifting mechanism being capable of being connected to a tool fixture bracket being configured to accommodate the tool fixture; a coating device including a coating chamber which a plane target mechanism and a turntable assembly disposed in, the turntable assembly is capable of being connected to a plurality of tool fixtures being capable of rotating around an axial line of the coating chamber under the driving of the turntable assembly and rotating around an axial line thereof at the same time; and, a manipulator being disposed between the cleaning device and the coating device.

Abstract: A multi-procedure integrated automatic production line for hard alloy blades under robot control is provided. The production line includes a rail-guided robot. A cutter passivation device and a blade cleaning and drying device are arranged on one side of the rail-guided robot. A blade-coating transfer table, a blade coating device, a blade boxing transfer table, a blade-tooling dismounting device and a blade boxing device are sequentially arranged on another side of the rail-guided robot. The blade-tooling dismounting device is arranged on one side of the blade boxing transfer table. The production line further includes squirrel-cage toolings for carrying the blades. The squirrel-cage tooling that are loaded with the blades can run among the cutter passivation device, the blade cleaning and drying device, the blade-coating transfer table and the blade boxing transfer table. The blades after being treated through the blade-tooling dismounting device are sent to the blade boxing device.

Abstract: The present invention discloses a high-entropy soft magnetic alloy with 900 K high-temperature resistance, comprising Fe, Co, Ni, Si and Al, and the atomic percent of the alloy composition is expressed as FexCoyNizSimAln, wherein x=40%-80%, y=20%-60%, z=0-30%, m=0-20%, n=0-20%, and x+y+z+m+n=100%; the atomic percent of other doping elements is p=0-5%, and 0.5?m/n?3; the performance indexes of the material include: at room temperature, saturation magnetization Ms=90-150 emu/g, and coercive force Hc=0.1-15 Oe; and at 900 K, saturation magnetization Ms=70-130 emu/g, and coercive force Hc=0.1-25 Oe.

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data.