Abstract: Provided are a MOSFET and a method for manufacturing the same. The method comprises: a. Providing a substrate (100), a dummy gate vacancy, a first spacer (150), source/drain extension regions (205), source/drain regions (200) and an interlayer dielectric layer (300); b. Depositing a silicon dioxide layer (160) in the dummy gate vacancy on the substrate; c. Depositing a gate dielectric layer (400) on the formed semiconductor structure; d. Forming a second spacer (450) in the dummy gate vacancy, wherein the second spacer (450) is adjacent to the gate dielectric layer (400) and is flushed with the interlayer dielectric layer (300); and e. Forming a gate stack (500) in the dummy gate vacancy . Negative effects caused by variation in thickness of the oxide layer under the gate can be eliminated, and device performance can be improved.

Abstract: A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.

Abstract: The present invention relates to enhancing MOSFET performance with the corner stresses of STI.

Abstract: A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i.

Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.

Abstract: The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.

Abstract: The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.

Abstract: A method for fabricating a FinFET DEVICE is provided in the invention, comprising: a. providing a substrate (100);b. forming a fin (200) on the substrate (200); c. depositing a doping material layer (300) on the semiconductor structure formed after the step b; d. forming a first shallow trench isolation (400) on the semiconductor formed after the step c; e. removing a portion of the doping material layer (300) which is not covered by the first shallow trench isolation (400); f. performing an annealing process to form a doped region (500) in a channel region which is in the middle portion of the fin; g. forming a second shallow trench isolation (600) on the semiconductor formed after the step f; h. forming a source region and a drain region in opposite portions of the fin and forming a gate stack on the middle portion of the fin. Comparing with the prior art, punch through effect will be restrained and process complexity will be reduced.

Abstract: A method for manufacturing a MOSFET, including: performing ion implantation, via a shallow trench surrounding an active region in a semiconductor substrate, into a first sidewall of the active region and into a second sidewall of the active region opposite to the first sidewall to form a first heavily doped region in the first sidewall and a second heavily doped region in the second sidewall; filling the shallow trench with an insulating material, to form a shallow trench isolation; forming a gate stack and an insulating layer on the substrate, wherein the insulating layer surrounds and caps the gate stack; forming openings in the substrate using the shallow trench isolation, the first and second heavily doped regions, and the insulating layer as a hard mask; and epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a seed layer.

Abstract: There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits.

Abstract: A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.

Abstract: The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

Abstract: Provided is a method for manufacturing a MOSFET, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the MOSFET; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions.

Abstract: The present invention provides a semiconductor structure, which comprises a semiconductor substrate and at least two semiconductor fins located on the semiconductor substrate, wherein: the at least two semiconductor fins are parallel to each other; and the parallel sidewall surfaces of the at least two semiconductor fins have different crystal planes. The present invention further provides a method for manufacturing aforesaid semiconductor structure.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.

Abstract: A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.