Abstract: A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output the peak signal, a comparator to compare the input signal and the peak signal to generate a clock signal, and said track and hold circuit to output the peak signal in accordance with the clock signal.

Abstract: A current limiting circuit to limit current including an input circuit to input an input voltage, a connecting circuit to connect the input voltage to a current, and a current limiting circuit controlled by a constant voltage to limit said current.

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output the peak signal, a comparator to compare the input signal and the peak signal to generate a clock signal, and said track and hold circuit to output the peak signal in accordance with the clock signal.

Abstract: A current limiting circuit to limit current including an input circuit to input an input voltage, a connecting circuit to connect the input voltage to a current, and a current limiting circuit controlled by a constant voltage to limit said current.

Abstract: A low-power dual-g.sub.m differential operational transconductance amplifier (OTA) having a differential input for improved common-mode noise rejection, a high transconductance for power savings, and circuitry for controlling its output conductance. The OTA includes a pair of input inverters for receiving differential input signals, a common-mode voltage control circuit for controlling the DC voltage levels of the inverters, and a Q-control circuit for adjusting the OTA's output conductance. The common-mode voltage control circuit has a pair of compensating current sources and a feedback loop acting as a high-gain amplifier. The high-gain amplifier has a pair of comparators for respectively comparing the DC voltage levels of the inverter outputs with a reference voltage. The Q-control circuit includes a current source coupled to a crossed-coupled NMOS transistor pair such that the OTA's output conductance may be controlled by adjusting the current source.

Abstract: An analog-to-digital (A/D) converter capable of receiving a differential input for improved noise rejection and having two static resistive ladders for reducing power consumption. The resistive ladders are anti-parallel and have a high impedance, each dividing fixed voltages into a group of reference voltages. A first stage of comparators compares the positive signal of the differential input with each of the reference voltages from one of the resistive ladder, and the negative input signal with each of the reference voltages from the other resistive ladder. The outputs of the first stage of comparators are compared by a second stage of comparators to generate a group of binary outputs in parallel. An encoder converts the outputs of the second-stage comparators into a digital value. Decoupling capacitors are also provided to reduce the AC impedance of the resistive ladders.

Abstract: An analog front end for signal processing circuit such as a hard-disk data read channel having a calibration circuit for canceling DC offset is described. First, the DC offset is cancelled from a positive phase input to an A/D converter (ADC). Second, a DC offset is cancelled separately from a negative phase input to the A/D converter. The combined positive and negative phases form an amplified analog signal that is used as the differential input to the A/D converter. Finally, the DC offset in a path that encompasses the system analog input through the system digital output is cancelled. Controlling the buffer amplifier bias makes trimming unnecessary. It also enables faster calibration. Further, the two differential phase lines, i.e., the positive phase line and the negative phase line, are each calibrated in turn. As such, a common calibration circuit may be used, thereby avoiding circuit duplication.