Patents by Inventor Hajime Ogawa

Hajime Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130325166
    Abstract: A numerical control device according to the present invention includes a display part for displaying a program coordinate and a command coordinate such that they can be compared with each other. The display part may be adapted to further display an actual coordinate. The display part may also be adapted to further display a program trajectory, a command trajectory and an actual trajectory, which are obtained from a machining program and the program coordinate, the command coordinate and the actual coordinate, respectively.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 5, 2013
    Applicant: FANUC Corparation
    Inventors: Junichi TEZUKA, Hajime OGAWA
  • Publication number: 20130271048
    Abstract: A second q-axis current command value, which is set by a q-axis current command value setting unit when an alternating-current power source fails at the time of driving of a synchronous motor, and a second d-axis current command value, which is set by a d-axis current command value setting unit when the alternating-current power source fails at the time of the driving of the synchronous motor, are set so that an absolute value of power per unit time of the synchronous motor is equal to loss per unit time of the synchronous motor.
    Type: Application
    Filed: February 28, 2013
    Publication date: October 17, 2013
    Applicant: FANUC CORPORATION
    Inventors: Yasusuke IWASHITA, Hajime OGAWA
  • Publication number: 20130099705
    Abstract: A motor driving device includes a converter that converts an input alternating current into a direct current, an inverter that inverts the direct current output by the converter into an alternating current for driving a motor, a voltage detecting unit that detects a voltage on a direct current output side of the converter, and a numerical control unit that causes the inverter to output a reactive current to increase electric power consumed in the motor, when the voltage detected by the voltage detecting unit exceeds a predetermined threshold.
    Type: Application
    Filed: August 27, 2012
    Publication date: April 25, 2013
    Applicant: FANUC CORPORATION
    Inventors: Yasusuke IWASHITA, Hajime OGAWA
  • Publication number: 20130096700
    Abstract: A numerical controller having a display function for comparing data at a predetermined position regardless of a change in a processing condition. The numerical controller comprises a numerical controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each axis and a tool representative point of the machine tool; a movement distance calculating part which calculates movement distance of the axis and the tool representative point based on the obtained position data and dimensional information of each component of the machine tool; a physical data obtaining part which obtains physical data of each axis and the tool; a data converting part which converts the obtained time axis-based physical data into movement distance-based data; a distance-based data storing part which stores the movement distance-based data; and a displaying part which displays the movement distance-based data.
    Type: Application
    Filed: September 10, 2012
    Publication date: April 18, 2013
    Applicant: FANUC Corporation
    Inventors: Junichi TEZUKA, Hajime OGAWA
  • Patent number: 8418157
    Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: April 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
  • Publication number: 20130076287
    Abstract: A numerical controller capable of visually and accurately analyzing a change of the tool trajectory before and after changing a processing condition, whereby a parameter of a drive axis can be properly adjusted. The numerical controller comprises a numeric controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each drive axis controlled by the numerical controlling part; a tool coordinate calculating part which calculates a coordinate of a tool center point based on position feedback or obtained position data of each drive axis and information of a mechanical structure of a machine tool; a tool trajectory storing part which stores the calculated coordinate of the tool center point as a feedback trajectory; and a displaying part which displays the stored feedback trajectory on a display.
    Type: Application
    Filed: August 2, 2012
    Publication date: March 28, 2013
    Applicant: FANUC Corporation
    Inventors: Yasusuke Iwashita, Hajime Ogawa
  • Publication number: 20130054182
    Abstract: A tool path display apparatus (20) includes a tool coordinate value calculation unit (22) that calculates tool commanded coordinate values and tool actual coordinate values, based on commanded value time series data of position commands for a plurality of axes, detected value time series data of position detected values for the plurality of axes, and the structure of a machine tool, an acceleration calculation unit (23) that calculates accelerations of a tip point of a tool using the tool commanded coordinate values and the tool actual coordinate values, and a display format selection unit (24) that selects display formats of the accelerations of the tool commanded coordinate values and the tool actual coordinate values.
    Type: Application
    Filed: June 26, 2012
    Publication date: February 28, 2013
    Applicant: FANUC CORPORATION
    Inventors: Junichi TEZUKA, Hajime OGAWA
  • Publication number: 20130030558
    Abstract: A numerical controller, wherein an operator, even remotely, can recognize a sound of a machine tool or the like, and can intuitively know the effect in adjusting the parameter. The numerical controller includes a drive axis controlling part configured to control a drive axis; a drive axis data storing part configured to obtain a physical quantity of the drive axis as time-series data and store the time-series data; a displaying part configured to convert the time-series data into a predetermined indication form and display the data as at least one displayed waveform; a selecting part configured to select the displayed waveform by input operation of the operator; a sound converting part configured to convert the selected waveform into sound conversion data, a type of which is capable of being output as sound; and a sound outputting part configured to output the generated sound conversion data as sound.
    Type: Application
    Filed: June 12, 2012
    Publication date: January 31, 2013
    Applicant: FANUC CORPORATION
    Inventors: Junichi TEZUKA, Hajime OGAWA
  • Publication number: 20120306413
    Abstract: A motor driving device comprises: a single DC conversion unit that converts input AC into DC; a plurality of AC conversion units that convert DC output from the DC conversion unit into AC supplied to a plurality of motor units as driving electric power; an electric power consumption calculation unit of the DC conversion unit that calculates electric power consumption of the DC conversion unit from the input voltage and input current to the DC conversion unit every predetermined time period; and a maximum output calculation unit of the DC conversion unit that extracts a maximum value from the electric power consumption of the DC conversion unit calculated every predetermined time period and outputs it as a maximum output of the DC conversion unit.
    Type: Application
    Filed: May 9, 2012
    Publication date: December 6, 2012
    Applicant: FANUC Corporation
    Inventors: Junichi TEZUKA, Hajime Ogawa
  • Publication number: 20120257276
    Abstract: A tool path display apparatus, configured to display a three-dimensional path of a movable part of a machine tool, calculates three-dimensional coordinate values of the movable part as viewed from a coordinate system secured to a workpiece, thereby determining the three-dimensional path of the movable part. Left- and right-eye stereoscopic image data are determined based on the determined three-dimensional path of the movable part, and the determined left- and right-eye stereoscopic image data are displayed on the display apparatus so that they can be viewed by an operator's left and right eyes, respectively.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 11, 2012
    Applicant: FANUC CORPORATION
    Inventors: Junichi TEZUKA, Hajime OGAWA
  • Patent number: 8286145
    Abstract: A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Teruo Kawabata, Masatsugu Daimon, Taketo Heishi, Hajime Ogawa
  • Patent number: 8151254
    Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: April 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
  • Patent number: 7856629
    Abstract: A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Shohei Michimoto, Taketo Heishi, Hajime Ogawa, Teruo Kawabata
  • Patent number: 7827542
    Abstract: A compiler apparatus that improves the performance of loop processing. The compiler apparatus translates a C program that includes a loop into a machine language program, and includes: a movement judgment unit that judges whether or not an instruction which is positioned outside of the loop of the C program can be moved into the loop, based on a state of live ranges of variables used in the instruction; a movement execution unit that moves the instruction into the loop in the case where the movement judgment unit judges that the instruction can be moved into the loop, thereby generating an intermediate program; and a translation unit that translates the intermediate program into the machine language program.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: November 2, 2010
    Assignee: Panasonic Corporation
    Inventors: Hajime Ogawa, Ryoko Miyachi, Toshiyuki Sakata
  • Patent number: 7823142
    Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Shuichi Takayama, Hajime Ogawa, Kenichi Kawaguchi, Nobuo Higaki, Kensuke Odani, Tetsuya Tanaka, Shinya Miyaji, Taketo Heishi
  • Patent number: 7761692
    Abstract: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Taketo Heishi, Shuichi Takayama, Tetsuya Tanaka, Hajime Ogawa, Nobuo Higaki
  • Publication number: 20100175056
    Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
    Type: Application
    Filed: February 16, 2010
    Publication date: July 8, 2010
    Inventors: Hajime OGAWA, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
  • Patent number: 7698696
    Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
  • Patent number: 7689976
    Abstract: A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Yamamoto, Hajime Ogawa, Taketo Heishi, Shohei Michimoto
  • Patent number: 7594099
    Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda