Abstract: A medical image processing apparatus according to an embodiment includes processing circuitry. The processing circuitry acquires a plurality of projection data based on an output signal from an X-ray detector that rotates around a subject, performs reconstruction filter processing on the plurality of acquired projection data, the reconstruction filter processing being included in reconstruction regarding the plurality of projection data, generates correction information on a sensitivity difference area formed in the plurality of projection data due to differences in sensitivity of the X-ray detector, on the basis of a processing result of the reconstruction filter processing, performs correction processing on the plurality of projection data on the basis of the correction information, and performs reconstruction processing including the reconstruction filter processing on the plurality of projection data subjected to the correction processing.

Abstract: A resolver signal processing device includes a deviation calculation unit, a PI operation unit, and an integration operation unit. The deviation calculation unit calculates a deviation between a first product obtained by multiplying a signal of phase A by a cosine value based on a reference phase ?ref and a second product obtained by multiplying a signal of phase B by a sine value based on the reference phase ?ref. The PI operation unit carries out a proportional integration operation which includes a first integration operation and is defined to converge the deviation on zero on the basis of the deviation. The integration operation unit carries out a second integration operation of integrating a value generated from a result of the proportional integration operation and outputs a result of the second integration operation as phase information of the resolver.

Abstract: Provided is a deterioration estimation device and a deterioration estimation program for a power conversion device that can estimate the deterioration of a switching element without providing a special sensor. A deterioration estimation device includes a calculating device calculating the variation of the characteristics of an IGBT in an inverter from a voltage command treated as a target of the output voltage of the power conversion device and the output voltage value of the power conversion device, a determining device determining whether the variation of the characteristics calculated by the calculating device has changed from an initial state by a threshold value or greater, and a notifying device issuing a warning when the determining device has determined that the change in the variation of the characteristics is equal to or greater than the threshold value.

Abstract: A resolver signal processing device includes a deviation calculation unit, a PI operation unit, and an integration operation unit. The deviation calculation unit calculates a deviation between a first product obtained by multiplying a signal of phase A by a cosine value based on a reference phase ?ref and a second product obtained by multiplying a signal of phase B by a sine value based on the reference phase ?ref. The PI operation unit carries out a proportional integration operation which includes a first integration operation and is defined to converge the deviation on zero on the basis of the deviation. The integration operation unit carries out a second integration operation of integrating a value generated from a result of the proportional integration operation and outputs a result of the second integration operation as phase information of the resolver.

Abstract: An inter-hierarchy synchronizing system and an LSI include a plurality of function blocks taking a hierarchical structure and having timing systems expressed by timing variables independent of each other and inter-hierarchy synchronizing blocks disposed these hierarchies. This synchronizing block has: an input event temporary storage part for receiving and storing an input event generation signal group from a higher-level block; an activation timing judging part for judging activations of a plurality of function blocks and transmitting activation signals; an output event temporary storage part for receiving and storing output event generation signals including a completion signal from lower-level blocks; and a final completion signal judging part for judging a final completion state on the basis of a signal from the output event temporary storage part and transmitting a final completion signal to the high-block.

Abstract: An application specific integrated circuit which can develop a wide variety of integrated circuits in a short time period is provided. In respective functional blocks, inheritance circuits capable of holding and transferring function inheritance information necessary for univocally specifying functions of respective corresponding functional blocks, bearer switches serving as a data transfer switch, and program wiring mechanisms are provided. After a mother wafer on which such units are hierarchically connected by function inheritance information read-out buses is manufactured, function inheritance information is read out to obtain, on the basis of the read out information, information for connecting partial circuit groups within block having one-to-one correspondence with respect to that information to drive programmable wiring mechanisms by using such information, thus to obtain connections as defined be the system requirement specification.

Abstract: It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.

Abstract: According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

Abstract: Strands of a copper alloy containing 0.2 to 10 percent by weight of Sn are braided to form a stranded wire for a wire conductor for a harness having a conductor sectional area of 0.03 to 0.3 mm.sup.2. After the braiding, preferably stranded wire is heat treated so that its tensile strength is maintained at a prescribed level. The wire conductor for a harness has a breaking strength which is equivalent to that of a conventional harness wire, and is hardly broken by an impact. The wire conductor maintains its straightness, and strand ends do not fray upon cutting.

Abstract: According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

Abstract: According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

Abstract: After detecting a leading edge of a stop control signal supplied from an external circuit, an oscillation output signal is cut off at an input side of a frequency divider in synchronism with the first leading edge of a clock signal generated from the frequency divider, thereby stopping the generation of clock signals. The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal is detected, an internal state of the frequency divider is initialized, and the oscillation output signal which has been cut off is supplied to the frequency divider again, thereby generating a proper clock signal.