Patents by Inventor Hak-kyoon Byun
Hak-kyoon Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9245863Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: GrantFiled: July 16, 2013Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-jung Yu, Hak-kyoon Byun, Kyung-tae Na, Seung-hun Han, Tae-sung Park, Choong-bin Yim
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Patent number: 9111926Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: GrantFiled: May 28, 2014Date of Patent: August 18, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Publication number: 20140264940Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Dae-Young CHOI, Mi-Yeon KIM
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Patent number: 8759967Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: GrantFiled: August 29, 2013Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Publication number: 20140091463Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: ApplicationFiled: July 16, 2013Publication date: April 3, 2014Inventors: Hae-jung YU, Hak-kyoon BYUN, Kyung-tae NA, Seung-hun HAN, Tae-sung PARK, Choong-bin YIM
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Publication number: 20140001649Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Patent number: 8531034Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: GrantFiled: September 25, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Publication number: 20120315726Abstract: Provided are methods of manufacturing a semiconductor chip package. The method includes forming a plurality of semiconductor chips, each of which includes a semiconductor substrate having a front and back surfaces facing each other, a chip pad provided on the front surface of the semiconductor substrate, and an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate, stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other, and reflowing the interconnection patterns of the semiconductor chips to connect the stacked semiconductor chips with each other.Type: ApplicationFiled: June 7, 2012Publication date: December 13, 2012Inventors: HAK-KYOON BYUN, Bu-Won Kim, Raehyung Do, JongBo Shim, Woodong Lee
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Patent number: 8304876Abstract: Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.Type: GrantFiled: August 12, 2009Date of Patent: November 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Kyoon Byun, Taehoon Kim, Jongkook Kim, Sang-Uk Han, Jung-Do Lee, Seonhyang You
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Publication number: 20120153499Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: September 25, 2011Publication date: June 21, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Dae-Young CHOI, Mi-Yeon KIM
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Patent number: 8184449Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.Type: GrantFiled: September 8, 2008Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Do Lee, Hak-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You
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Patent number: 7795743Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.Type: GrantFiled: October 5, 2006Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hun Kim, Hak-Kyoon Byun, Sung-Yong Park, Heung-Kyu Kwon
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Publication number: 20100038765Abstract: Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.Type: ApplicationFiled: August 12, 2009Publication date: February 18, 2010Inventors: Hak-Kyoon Byun, Taehoon Kim, Jongkook Kim, Sang-Uk Han, Jung-Do Lee, Seonhyang You
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Publication number: 20100037445Abstract: An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.Type: ApplicationFiled: October 22, 2009Publication date: February 18, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youn-sung Ko, Hak-kyoon Byun, Jung-hwan Woo, Hyun-jung Song
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Patent number: 7624498Abstract: An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.Type: GrantFiled: May 30, 2007Date of Patent: December 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-sung Ko, Hak-kyoon Byun, Jung-hwan Woo, Hyun-jung Song
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Patent number: 7541680Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.Type: GrantFiled: August 25, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-kyu Kwon, Se-nyun Kim, Tae-hun Kim, Jeong-o Ha, Hak-kyoon Byun, Sung-yong Park
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Publication number: 20090085185Abstract: A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.Type: ApplicationFiled: September 26, 2008Publication date: April 2, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Tae-Hun KIM, Sang-Uk HAN, Jung-Do LEE, Seon-Hyang YOU
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Publication number: 20090067143Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.Type: ApplicationFiled: September 8, 2008Publication date: March 12, 2009Inventors: Jung-Do Lee, Hak-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You
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Publication number: 20080160725Abstract: According to example embodiments, an apparatus for picking up a semiconductor die includes an electromagnetic collet unit configured to selectively generate an attractive force between the electromagnetic collet unit and a magnetic wafer adhesive tape disposed on a surface of the semiconductor die. The apparatus further includes a transfer head unit attached to the electromagnetic collet unit, the transfer head unit structured to move the semiconductor die picked up by the collet unit through a drive of a drive device.Type: ApplicationFiled: December 18, 2007Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Hyun-Jung SONG, Jong-Bo SHIM
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Publication number: 20080160724Abstract: Provided is a method of dicing a wafer where a plurality of semiconductor device regions is formed on a front side of the wafer, the semiconductor device regions being separated by scribe lanes, the method comprising dicing the wafer by irradiating a laser beam on a backside of the wafer along the scribe lanes. A laser beam is irradiated from an opposite side of the semiconductor device regions of the wafer so that thermal influence on the semiconductor device regions is minimized to improve the strength of a semiconductor chip. Furthermore, a third tape is used to maintain an arrangement of the semiconductor chips so as to minimize adherence problems caused by the laser beam.Type: ApplicationFiled: November 27, 2007Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jung SONG, Hak-Kyoon BYUN, Jong-Bo SHIM, Min-Ok NA