Patents by Inventor Hamilton Lu
Hamilton Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10546750Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: GrantFiled: January 5, 2016Date of Patent: January 28, 2020Assignee: Vishay-SiliconixInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 9704858Abstract: An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.Type: GrantFiled: July 9, 2015Date of Patent: July 11, 2017Assignee: O2Micro, Inc.Inventors: Hamilton Lu, Laszlo Lipcsei
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Publication number: 20170012040Abstract: An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.Type: ApplicationFiled: July 9, 2015Publication date: January 12, 2017Inventors: Hamilton LU, Laszlo LIPCSEI
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Publication number: 20160225622Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: ApplicationFiled: January 5, 2016Publication date: August 4, 2016Applicant: Vishay-SiliconixInventors: Hamilton LU, The-Tu CHAU, Kyle TERRILL, Deva N. PATTANAYAK, Sharon SHI, Kuo-In CHEN, Robert XU
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Patent number: 9230810Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: GrantFiled: August 31, 2010Date of Patent: January 5, 2016Assignee: Vishay-SiliconixInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 8754472Abstract: A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.Type: GrantFiled: March 10, 2011Date of Patent: June 17, 2014Assignee: O2Micro, Inc.Inventors: Hamilton Lu, Laszlo Lipcsei
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Publication number: 20120228699Abstract: A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Applicant: O2MICRO, INC.Inventors: Hamilton Lu, Laszlo Lipcsei
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Publication number: 20120028425Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) can be fabricated in an upward direction. A trench bottom doping (TBD) process and/or a trench bottom oxide (TBO) process can be performed after formation of a substrate and a first epitaxial (epi) layer. Poly seal can be performed after the formation of TBO layers and before a merged epitaxial lateral overgrowth (MELO) step to improve quality and purity of a second epi layer formed in the MELO step. Plasma dry etching with an end point mode can be performed according to the locations of TBO layers to improve the uniformity of trench depth.Type: ApplicationFiled: June 27, 2011Publication date: February 2, 2012Inventors: Hamilton LU, Laszlo LIPCSEI
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Publication number: 20110108912Abstract: A method for fabricating a cellular trench metal oxide semiconductor field effect transistor (MOSFET) includes depositing a first photoresist atop a first epitaxial (epi) layer to pattern a trench area, depositing a second photoresist atop a first gate conductor layer to pattern a mesa area, etching away part of the first gate conductor layer in the mesa area to form a second gate conductor layer with a hump, and titanizing crystally the second gate conductor layer to form a Ti-gate conductor layer. Edges of the mesa area are aligned to edges of the trench area. Hence, approximately more than half of polysilicon in the second gate conductor layer is titanized crystally. A spacer can be formed to protect corners of the first gate conductor layer and to make the gate conductor structure more robust for mechanical support.Type: ApplicationFiled: October 15, 2010Publication date: May 12, 2011Inventors: Hamilton LU, Laszlo LIPCSEI
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Publication number: 20110049682Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: VISHAY-SILICONIXInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 7507608Abstract: The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.Type: GrantFiled: December 8, 2005Date of Patent: March 24, 2009Assignee: International Rectifier CorporationInventors: Richard Francis, Chiu Ng, Hamilton Lu, Ranadeep Dutta
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Publication number: 20060094179Abstract: The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.Type: ApplicationFiled: December 8, 2005Publication date: May 4, 2006Inventors: Richard Francis, Chiu Ng, Hamilton Lu, Ranadeep Dutta
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Patent number: 7005702Abstract: The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.Type: GrantFiled: May 5, 2000Date of Patent: February 28, 2006Assignee: International Rectifier CorporationInventors: Richard Francis, Chiu Ng, Hamilton Lu, Ranadeep Dutta
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Publication number: 20030168695Abstract: The tops of the conductive polysilicon gates of a trench device have a layer of a silicide such as titanium silicide which is more conductive than the polysilicon gate, thereby reducing gate resistance.Type: ApplicationFiled: March 7, 2003Publication date: September 11, 2003Applicant: International Rectifier Corp.Inventors: Ritu Sodhi, Hamilton Lu, Milton J. Boden
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Patent number: 6602786Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.Type: GrantFiled: February 21, 2002Date of Patent: August 5, 2003Assignee: International Rectifier CorporationInventor: Hamilton Lu
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Publication number: 20020132456Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.Type: ApplicationFiled: February 21, 2002Publication date: September 19, 2002Applicant: International Rectifier Corp.Inventor: Hamilton Lu