Patents by Inventor Han-Chee Yen
Han-Chee Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194609Abstract: An electronic device is disclosed. The electronic device includes a first component, a second component, and a first bridge component configured to electrically connect the first component with the second component. The first component is configured to transmit a first signal downwardly without passing the first bridge component and the second component is configured to transmit/receive a second signal to/from outside of the electronic device. A transmission speed of the second signal is higher than a transmission speed of the first signal.Type: ApplicationFiled: December 7, 2022Publication date: June 13, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG, Eelco BERGMAN
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Patent number: 11848296Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.Type: GrantFiled: October 26, 2021Date of Patent: December 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
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Publication number: 20230400648Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee YEN, Min-Yao CHENG, Hung-Yi LIN
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Publication number: 20230299462Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Han-Chee YEN
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Patent number: 11664580Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.Type: GrantFiled: November 29, 2017Date of Patent: May 30, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Han-Chee Yen
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Publication number: 20220052013Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.Type: ApplicationFiled: October 26, 2021Publication date: February 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
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Patent number: 11239178Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.Type: GrantFiled: November 25, 2019Date of Patent: February 1, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chanyuan Liu, Han-Chee Yen, Kuo-Hsien Liao, Alex Chi-Hong Chan, Christophe Zinck
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Patent number: 11158596Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.Type: GrantFiled: March 20, 2020Date of Patent: October 26, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
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Publication number: 20210296278Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
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Patent number: 10811763Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.Type: GrantFiled: April 11, 2018Date of Patent: October 20, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Han-Chee Yen
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Publication number: 20200176394Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.Type: ApplicationFiled: November 25, 2019Publication date: June 4, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chanyuan LIU, Han-Chee YEN, Kuo-Hsien LIAO, Alex Chi-Hong CHAN, Christophe Zinck
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Publication number: 20190319337Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.Type: ApplicationFiled: April 11, 2018Publication date: October 17, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Han-Chee YEN
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Patent number: 9978688Abstract: A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna.Type: GrantFiled: February 28, 2013Date of Patent: May 22, 2018Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
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Publication number: 20180083341Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.Type: ApplicationFiled: November 29, 2017Publication date: March 22, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Han-Chee YEN
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Patent number: 9837701Abstract: A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.Type: GrantFiled: March 4, 2013Date of Patent: December 5, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Han-Chee Yen
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Patent number: 9153542Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.Type: GrantFiled: August 1, 2012Date of Patent: October 6, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: I-Chia Lin, Sheng-Jian Jou, Han-Chee Yen
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Patent number: 9129954Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a package body and an antenna layer. The semiconductor chip is disposed on the substrate. The package body encapsulates the semiconductor chip and includes an upper surface. The antenna layer is formed on the upper surface of the package body and includes two antenna slot groups connected together. Each antenna slot group includes a wave guiding slot extending along a first direction, and an irradiation slot group extending along a second direction, wherein the irradiation slot group is connected to the wave guiding slot.Type: GrantFiled: March 7, 2013Date of Patent: September 8, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
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Publication number: 20140252595Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a package body and an antenna layer. The semiconductor chip is disposed on the substrate. The package body encapsulates the semiconductor chip and includes an upper surface. The antenna layer is formed on the upper surface of the package body and includes two antenna slot groups connected together. Each antenna slot group includes a wave guiding slot extending along a first direction, and an irradiation slot group extending along a second direction, wherein the irradiation slot group is connected to the wave guiding slot.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
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Publication number: 20140247195Abstract: A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Han-Chee Yen
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Publication number: 20140239465Abstract: A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng