Patents by Inventor Han-Chee Yen

Han-Chee Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194609
    Abstract: An electronic device is disclosed. The electronic device includes a first component, a second component, and a first bridge component configured to electrically connect the first component with the second component. The first component is configured to transmit a first signal downwardly without passing the first bridge component and the second component is configured to transmit/receive a second signal to/from outside of the electronic device. A transmission speed of the second signal is higher than a transmission speed of the first signal.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 13, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG, Eelco BERGMAN
  • Patent number: 11848296
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
  • Publication number: 20230400648
    Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Min-Yao CHENG, Hung-Yi LIN
  • Publication number: 20230299462
    Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 21, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Han-Chee YEN
  • Patent number: 11664580
    Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 30, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Han-Chee Yen
  • Publication number: 20220052013
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
  • Patent number: 11239178
    Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chanyuan Liu, Han-Chee Yen, Kuo-Hsien Liao, Alex Chi-Hong Chan, Christophe Zinck
  • Patent number: 11158596
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
  • Publication number: 20210296278
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
  • Patent number: 10811763
    Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 20, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Han-Chee Yen
  • Publication number: 20200176394
    Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chanyuan LIU, Han-Chee YEN, Kuo-Hsien LIAO, Alex Chi-Hong CHAN, Christophe Zinck
  • Publication number: 20190319337
    Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Han-Chee YEN
  • Patent number: 9978688
    Abstract: A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 22, 2018
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
  • Publication number: 20180083341
    Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Han-Chee YEN
  • Patent number: 9837701
    Abstract: A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 5, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Han-Chee Yen
  • Patent number: 9153542
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: October 6, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Sheng-Jian Jou, Han-Chee Yen
  • Patent number: 9129954
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a package body and an antenna layer. The semiconductor chip is disposed on the substrate. The package body encapsulates the semiconductor chip and includes an upper surface. The antenna layer is formed on the upper surface of the package body and includes two antenna slot groups connected together. Each antenna slot group includes a wave guiding slot extending along a first direction, and an irradiation slot group extending along a second direction, wherein the irradiation slot group is connected to the wave guiding slot.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 8, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
  • Publication number: 20140252595
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a package body and an antenna layer. The semiconductor chip is disposed on the substrate. The package body encapsulates the semiconductor chip and includes an upper surface. The antenna layer is formed on the upper surface of the package body and includes two antenna slot groups connected together. Each antenna slot group includes a wave guiding slot extending along a first direction, and an irradiation slot group extending along a second direction, wherein the irradiation slot group is connected to the wave guiding slot.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng
  • Publication number: 20140247195
    Abstract: A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Han-Chee Yen
  • Publication number: 20140239465
    Abstract: A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Shih-Yuan Chen, Chien-Pai Lai, Ming-Hsien Cheng