Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 ?m and a height between 1 and 500 ?m.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: The advantage of narrow-bandgap Sb-based devices is the realization of high-frequency operation with much lower power consumption. However, some properties such as chemical stability are the key issues for developing Sb-based devices. The process temperature of the ion implant and thermal annealing in conventional silicon industry is over 1000° C. Sb-based materials are easily degraded at temperature greater 300° C. Thus, this invention provides three processes for self-aligned gate with lower process temperature (<300° C.) to reduce device access region resistance and maintain material quality.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: The invention provides two Sb-based n- or p-channel layer structures as a template for MISFET and complementary MISFET development. Four types of MISFET devices and two types of complementary MISFET circuit devices can be developed based on the invented layer structures. Also, the layer structures can accommodate more than one complementary MISFETs and more than one single active MISFETs to be integrated on the same substrate monolithically.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.