Abstract: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

Abstract: A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

Abstract: Disclosed are a spin injection device applicable as a memory and a logical device using a spin valve effect obtained by injecting a carrier spin-polarized from a ferromagnet into a semiconductor at an ordinary temperature, and a spin-polarized field effect transistor.

Abstract: A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Abstract: The object of this invention is to provide a semiconductor wafer cleaning apparatus designed to clean several wafers at the same time while rotating the wafers held in a horizontal, laid-down position. In an operation of this apparatus, a wafer feeding robot arm 20 feeds wafers 60 from a wafer cassette 10 to a wafer boat 50 and seats the wafers in the wafer boat while maintaining a horizontal, laid-down position of the wafers. The wafer boat 50, with the horizontally laid-down wafers 60, is vertically moved downward by a boat drive unit 40 to be immersed in a wafer cleaning liquid flowing in a wafer cleaning bath 30. Thereafter, the boat 50 is rotated within the wafer cleaning liquid, and so the wafers 60 are washed and cleaned by the wafer cleaning liquid while being maintained in the horizontal, laid-down position and being rotated horizontally.

Abstract: A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Abstract: The object of this invention is to provide a semiconductor wafer cleaning apparatus designed to clean several ten wafers at the same time while rotating the wafers held in a horizontal, laid-down position. In an operation of this apparatus, a wafer feeding robot arm 20 feeds wafers 60 from a wafer cassette 10 to a wafer boat 50 and seats the wafers in the wafer boat while maintaining a horizontal, laid-down position of the wafers. The wafer boat 50, with the horizontally laid-down wafers 60, is vertically moved downward by a boat drive unit 40 to be immersed in a wafer cleaning liquid flowing in a wafer cleaning bath 30. Thereafter, the boat 50 is rotated within the wafer cleaning liquid, and so the wafers 60 are washed and cleaned by the wafer cleaning liquid while being maintained in the horizontal, laid-down position and being rotated horizontally.