Abstract: A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.

Abstract: A decoding apparatus in an Orthogonal Frequency Division Multiple Access (OFDMA) mobile communication system is provided. In the apparatus comprises, a first combiner performs first combining on an input burst a first number of times. A deinterleaver deinterleaves an output of the first combiner and outputs a burst having a repeated structure. A second combiner performs second combining on the burst having the repeated structure a second number of times. A decoder decodes the combined burst. A signal detector stores a second internal memory state value of the decoder for an instance where a first decoded bit is extracted from the decoded data, stores a second internal memory state value of the decoder for an instance where a last decoded bit is extracted from the decoded data, compares the first and second stored internal memory state values of the decoder, and sets a burst quality indicator (BQI) according to the comparison result.

Abstract: A method and apparatus for decoding a concatenated burst in a WiBro system are provided. A concatenated decoder fragments a received burst into fragment blocks, decodes at least one of the fragment blocks, and determines whether the decoded fragment block satisfies a circular state. A concatenated decoding controller determines burst quality information of the received burst according to a circular state check result on the decoded fragment block, and determines whether to stop decoding on the received burst according to the burst quality information.

Abstract: A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N?K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N?k) columns. The parity part is divided into P×P subblocks. P is a divisor of (N?K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.

Abstract: A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.

Abstract: A method and apparatus are provided for decoding a forward error correction code in a mobile communication system using a LDPC code. A check node processor performs check node processing on information received with a plurality of check nodes and an accumulator accumulates check node output values from the check node processor with previous accumulated values. An edge memory stores the check node output values, and two accumulation memories separately store accumulated values from the accumulator and the previous accumulated values. A subtractor subtracts the check node output values from the accumulated values, and a hard-decision block performs hard-decision on the received information and the output value of the subtractor. A bit buffer stores the hard-decision result, and a parity check block performs parity check on the hard-decision result to determine whether to stop iterative decoding. A multiplexer delivers the subtraction result values to both the check node processor and the hard-decision block.

Abstract: An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.