Patents by Inventor Han Shen

Han Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162109
    Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 16, 2024
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Kuo-Chung Yee, Yu-Jen Lien, Ke-Han Shen, Wei-Kong Sheng, Chung-Shi Liu, Szu-Wei Lu, Tsung-Fu Tsai, Chung-Ju Lee, Chih-Ming Ke
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11971565
    Abstract: An absorption type near-infrared filter comprising a first multilayer film, a second multilayer film, and an absorption film, wherein in the ultraviolet band, the difference of between the wavelength with the transmittance at 80% of the absorbing film and the wavelength with the reflectivity at 80% of the first multilayer film falls in the range between 25 nm and 37 nm, the difference of between the wavelength with the transmittance at 50% of the absorbing film and the wavelength with the reflectivity at 50% of the first multilayer film falls in the range between 6 nm and 14 nm, and the difference of between the wavelength with the transmittance at 20% of the absorbing film and the wavelength with the reflectivity at 20% of the first multilayer film falls in the range between ?6 nm and 2.5 nm.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 30, 2024
    Assignees: PTOT (SUZHOU) INC., PLATINUM OPTICS TECHNOLOGY INC.
    Inventors: Chung-Han Lu, Hsiao-Ching Shen, Chun-Cheng Hsieh, Ming-Zhan Wang
  • Publication number: 20240126123
    Abstract: This disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a first substrate, a second substrate, a first supporting member and a plurality of second supporting members. The first supporting member and the second supporting members are disposed between the first substrate and the second substrate. The first supporting member includes a first bottom surface and a first top surface. The second supporting member is disposed adjacent to the first supporting member and includes a second bottom surface and a second top surface. The difference between the radius of the first bottom surface and the radius of the first top surface is defined as a first radius bias. The difference between the radius of the second bottom surface and the radius of the second top surface is defined as a second radius bias. The first radius bias is greater than the second radius bias.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Chiung-Chieh KUO, Chi-Han HSIEH, Hsiang-Wen HSUEH, Shu-Hung SHEN
  • Publication number: 20240128149
    Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chieh HSIEH, Wei-Kong SHENG, Ke-Han SHEN, Yu-Jen LIEN
  • Patent number: 11954175
    Abstract: Disclosed herein is an improvement to prior art feature pyramids for general object detection that inserts a simple norm calibration (NC) operation between the feature pyramids and detection head to alleviate and balance the norm bias caused by feature pyramid network (FPN) and which leverages an enhanced multi-feature selective strategy (MS) during training to assign the ground-truth to one or more levels of the feature pyramid.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Carnegie Mellon University
    Inventors: Fangyi Chen, Chenchen Zhu, Zhiqiang Shen, Han Zhang, Marios Savvides
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20240088223
    Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Wen SHEN, Yen-Po Lin, Chun-Han Chen
  • Publication number: 20240078684
    Abstract: Certain aspects of the present disclosure provide techniques for global motion modeling. Embodiments include receiving a first image and a second image from a camera attached to a moving object. Embodiments include identifying a pixel in the first image. Embodiments include determining, based on one or more parameters associated with the camera, a vector representing a range of locations in which a real-world point corresponding to the pixel is likely to be found in the second image, wherein the parameters associated with the camera comprise: a first parameter related to a location of the camera relative to a ground surface; a second parameter related to motion of the moving object; and a third parameter related to an orientation of the camera relative to the ground surface. Embodiments include determining, using the vector, a location of the real-world point in the second image.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: Louis Joseph KEROFSKY, Geert VAN DER AUWERA, Marta KARCZEWICZ, Kuan-Ting SHEN, Dangdang SHAO, Khalid TAHBOUB, Bing HAN
  • Patent number: 11869054
    Abstract: Method and system to facilitate transactions in a particular on-line trading platform from a third party web site may be utilized beneficially to enhance a user's experience in purchasing items referenced on third party web pages. When a user encounters, on a third party web site, a presentation of an item that is linked to a listing maintained by the on-line trading platform, the user may simply click on the presentation of the item, which causes presentation of a visual control selectable to launch a transaction processing flow facilitated by the on-line trading platform, without requiring the user to leave the third party web site.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: January 9, 2024
    Assignee: EBAY INC.
    Inventors: Marc Peter Hosein, Selina Lam, Han-Shen Yuan
  • Publication number: 20230282482
    Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
    Type: Application
    Filed: June 4, 2022
    Publication date: September 7, 2023
    Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20230274938
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 31, 2023
    Inventors: Hao-Ming TANG, Shu-Han CHEN, Yun-San CHIEN, Da-Yuan LEE, Chi On CHUI, Tsung-Ju CHEN, Yi-Hsin TING, Han-Shen WANG
  • Publication number: 20230231037
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Patent number: 11610982
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Patent number: 11543958
    Abstract: An indication of a touch on a touch-enabled screen of a device is received that indicates a selection of a date facet in a listing of items. The date facet denotes a temporal indicator, other facets denote non-temporal indicators. An indication of a pinch gesture is received. The date facet is scaled to produce a scaled-facet listing. The scaling includes modifying a degree of a characteristic of the date facet in an increasing amount including producing a scaled-out listing implemented as an updated portion of item data having a different temporal indicator than an initial display of the item data by an amount proportional to a magnitude of a pinch gesture characteristic of the pinch gesture. The scaled-facet listing is displayed by exposing an updated set of the item data having the modified degree of the characteristic and replacing previous item data with the scaled-out listing.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: January 3, 2023
    Assignee: eBay Inc.
    Inventors: Han-Shen Yuan, Ryan Melcher, Steve Yankovich
  • Patent number: 11480210
    Abstract: A thermal concrete wing nut anchor includes a screw having an external thread, and a wing nut mounted on the screw. The screw has a first end provided with an enlarged stop flange, and a second end provided with a drilling tip. The stop flange is provided with a driving head. The wing nut is made of a metal sheet plate which is formed integrally by pressing. The wing nut has a middle provided with a first ear and at least one second ear. The wing nut has an internal thread extending through the first ear and the at least one second ear. The external thread of the screw is screwed through the internal thread of the wing nut.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: October 25, 2022
    Inventors: Po-Han Shen, Arthur Liao
  • Publication number: 20220318872
    Abstract: Method and system to facilitate transactions in a particular on-line trading platform from a third party web site may be utilized beneficially to enhance a user's experience in purchasing items referenced on third party web pages. When a user encounters, on a third party web site, a presentation of an item that is linked to a listing maintained by the on-line trading platform, the user may simply click on the presentation of the item, which causes presentation of a visual control selectable to launch a transaction processing flow facilitated by the on-line trading platform, without requiring the user to leave the third party web site.
    Type: Application
    Filed: June 15, 2022
    Publication date: October 6, 2022
    Inventors: Marc Peter Hosein, Selina Lam, Han-Shen Yuan
  • Patent number: 11379894
    Abstract: Method and system to facilitate transactions in a particular on-line trading platform from a third party web site may be utilized beneficially to enhance a user's experience in purchasing items referenced on third party web pages. When a user encounters, on a third party web site, a presentation of an item that is linked to a listing maintained by the on-line trading platform, the user may simply click on the presentation of the item, which causes presentation of a visual control selectable to launch a transaction processing flow facilitated by the on-line trading platform, without requiring the user to leave the third party web site.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: July 5, 2022
    Assignee: EBAY INC.
    Inventors: Marc Peter Hosein, Selina Lam, Han-Shen Yuan
  • Publication number: 20220173083
    Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Han Shen, Chen-Shien Chen, Kuo-Chio Liu, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20220085187
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Application
    Filed: January 4, 2021
    Publication date: March 17, 2022
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui