Patents by Inventor Han-Ti Hsiaw
Han-Ti Hsiaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220328316Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Patent number: 11380549Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: GrantFiled: July 27, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Publication number: 20210296160Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
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Patent number: 11031280Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.Type: GrantFiled: April 4, 2018Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
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Patent number: 10978341Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: December 5, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20200357645Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Patent number: 10727066Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: GrantFiled: November 19, 2019Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Publication number: 20200111705Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20200090939Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Patent number: 10510593Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: January 12, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Patent number: 10504734Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: GrantFiled: November 30, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Patent number: 10269569Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: GrantFiled: October 13, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Publication number: 20190096678Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Publication number: 20180226291Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: April 4, 2018Publication date: August 9, 2018Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
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Publication number: 20180151425Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: ApplicationFiled: January 12, 2018Publication date: May 31, 2018Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20180151373Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: ApplicationFiled: October 13, 2017Publication date: May 31, 2018Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Publication number: 20180145131Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Kuan-Cheng Wang, Han-Ti Hsiaw
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Patent number: 9960074Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.Type: GrantFiled: September 6, 2016Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
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Patent number: 9881834Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: March 17, 2017Date of Patent: January 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20180005870Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: September 6, 2016Publication date: January 4, 2018Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai