Patents by Inventor Han-Ting Yen
Han-Ting Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190067477Abstract: A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Inventors: Shi-You Liu, Ming-Shiou Hsieh, Rong-Sin Lin, Han-Ting Yen, Tsai-Yu Wen, Ching-I Li
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Patent number: 9966434Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: GrantFiled: June 26, 2017Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Publication number: 20180108570Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: ApplicationFiled: November 19, 2017Publication date: April 19, 2018Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9947588Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: November 19, 2017Date of Patent: April 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9859164Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: October 17, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Publication number: 20170330937Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: ApplicationFiled: June 26, 2017Publication date: November 16, 2017Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Patent number: 9722030Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: GrantFiled: June 7, 2016Date of Patent: August 1, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Publication number: 20140238837Abstract: A continuous type wastewater purifying device includes a wastewater tank defining a predetermined level of wastewater received in the wastewater tank. A purifying piping unit is mounted on a base and includes a wastewater pipe, a purified water pipe, and at least one heat conduction pipe having an inlet end and an outlet end respectively connected to and in communication with the wastewater pipe and the purified water pipe. The wastewater pipe has a first height from a mounting portion of the base in a height direction. The purified water pipe has a second height from the mounting portion in the height direction. The second height is greater than the first height. The inlet end and the outlet end of the at least one heat conduction pipe has a height difference therebetween. The outlet end of the at least one heat conduction pipe is higher than the predetermined level.Type: ApplicationFiled: August 28, 2013Publication date: August 28, 2014Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Jeng-Shiung Jan, Han-Ting Yen, Shuang-Yuan Chang, Meng-Hao Chuang, Shih-Kai Chou