Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: A styrene-modified polyethylene-based expandable resin particle is provided, which comprise a polyethylene resin and a polystyrene resin, wherein a content of the polyethylene resin ranges from 5 wt % to 30 wt % and a content of the polystyrene resin ranges from 70 wt % to 95 wt % based on 100 wt % of the polyethylene resin and the polystyrene resin, wherein the expandable resin particle comprises a xylene insoluble matter and an acetone insoluble matter, and a ratio of a content of the xylene insoluble matter to a content of the acetone insoluble matter ranges from 0.01 to 5. In addition, an expanded resin particle and a foamed resin molded article prepared by the aforesaid expandable resin particle are also provided. Furthermore, a method for manufacturing the aforesaid expandable resin particle is also provided.

Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.

Abstract: A preparation method of a lithium iron phosphate cathode material includes steps of (a) providing a phosphoric acid, an iron powder, a carbon source, wherein the phosphoric acid and the iron powder are reacted to produce a first product, and the first product is amorphous iron phosphate with chemical formula of a-FePO4·xH2O (x>0); (b) providing a lithium salt mixture, wherein the lithium salt mixture includes a lithium hydroxide and a lithium carbonate; (c) grinding and mixing the first product, the carbon source, and the lithium salt mixture; (d) calcining the first product and the lithium salt mixture to produce a precursor, wherein the precursor has a formula of Fe3(PO4)2·8H2O+Li3PO4; and (e) calcining the precursor and the carbon source to obtain the lithium iron phosphate cathode material.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

Abstract: The various technologies presented herein relate to pertaining to identifying and mitigating risks and attacks on a supply chain. A computer-implemented representation of a supply chain is generated comprising nodes (locations) and edges (objects, information). Risk to attack and different attack vectors can be defined for the various nodes and edges, and further, based upon the risks and attacks, (difficulty, consequence) pairs can be determined. One or more mitigations can be generated to increase a difficulty of attack and/or reduce consequence of an attack. The one or more mitigations can be constrained, e.g., by cost, time, etc., to facilitate determination of how feasible a respective mitigation is to implement with regard to finances available, duration to implement, etc. A context-free grammar can be utilized to identify one or more attacks in the supply chain. Further, the risks can undergo a ranking to enable mitigation priority to be determined.

Abstract: A filter includes a first housing having a first signal input terminal and a first signal output terminal, and a second housing having a second signal input terminal and a second signal output terminal. The second housing is stacked on and against the first housing.