Abstract: A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.

Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

Abstract: A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed.

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract: Disclosed is a program method of a non-volatile memory device which comprises classifying plural memory cells into aggressor cells and victim cells based on program data to be written in the plural memory cells; and programming the aggressor cells by a program manner different from the victim cells.

Abstract: An interference signal removing apparatus of a radio frequency (RF) receiver includes a low noise amplification unit which performs low noise amplification, a feedback processing unit which removes a necessary signal in a desired band from a signal output from the low noise amplification unit, and performs feedback of the signal from which the necessary signal is removed, and a signal processing unit which transmits a processed RF signal by synthesizing an input RF signal and the feedback signal to the noise amplification unit.

Abstract: Methods of accessing storage devices. The methods include rearranging a writing order of continuous first and second data according to a reading order, and writing the first and second data in a first and second storage region of the storage device, respectively, according to the writing order. The reading order reads the second storage region first that provides interference on the first storage region.

Abstract: A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.

Abstract: A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read data, and estimating a distribution characteristic for at least one of the overlapping threshold voltage distributions using the read index data.

Abstract: Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels.

Abstract: A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed.

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract: A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.

Abstract: A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data.

Abstract: A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.

Abstract: The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution.

Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

Abstract: Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.

Abstract: Methods of accessing storage devices. The methods include rearranging a writing order of continuous first and second data according to a reading order, and writing the first and second data in a first and second storage region of the storage device, respectively, according to the writing order. The reading order reads the second storage region first that provides interference on the first storage region.

Abstract: Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell.