Patents by Inventor Hanae Hata

Hanae Hata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8633103
    Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.
    Type: Grant
    Filed: June 13, 2010
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Hata, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
  • Publication number: 20110012263
    Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.
    Type: Application
    Filed: June 13, 2010
    Publication date: January 20, 2011
    Inventors: Hanae HATA, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
  • Publication number: 20100309641
    Abstract: A method of forming narrow-pitch flip-chip bonding electrodes and wire bonding electrodes at the same time is provided so as to reduce the cost of a substrate. In addition, a low-cost solder supply method and a flip-chip bonding method to a thin Au layer are provided. A stacked layer of a Cu layer 23 and a Ni layer 24 is employed as the electrode structure, and an Au layer 25 is plated on the outer periphery thereof. In the flip-chip bonding, dissolution of Au into the solder is minimized by employing a metal jet system in the soldering to the electrodes, so that the formation of Sn—Au having a high melting point is prevented, and at the same time, the wire-bondable Au layer 25 is ensured.
    Type: Application
    Filed: March 21, 2008
    Publication date: December 9, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hanae Hata, Masato Nakamura, Masaki Nakanishi, Nobuhiro Kinoshita
  • Patent number: 7722962
    Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, legal representative, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
  • Publication number: 20060145352
    Abstract: In an electronic device which realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a bonding portion between a semiconductor device and a substrate is formed of metal balls made of Cu, or the like, and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: January 23, 2006
    Publication date: July 6, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20060061974
    Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.
    Type: Application
    Filed: December 19, 2001
    Publication date: March 23, 2006
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
  • Patent number: 6872465
    Abstract: In a solder that realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a connection portion between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20040177997
    Abstract: It is an object of the present invention to provide an electronic device using completely new soldered connection, and more particularly to achieve flip chip bonding on a high temperature side in a temperature hierarchy connection as an alternative method for high Pb containing solder including a large mount of Pb. The object can be achieved by using a configuration in which metallic balls including a single metal, an alloy, a chemical compound or a mixture thereof are connected by Sn or In for pads between a chip and a substrate.
    Type: Application
    Filed: April 29, 2004
    Publication date: September 16, 2004
    Inventors: Hanae Hata, Tasao Soga, Toshiharu Ishida, Kazuma Miura, Kanko Ishida
  • Publication number: 20040007384
    Abstract: In an electronic device which realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a bonding portion between a semiconductor device and a substrate is formed of metal balls made of Cu, or the like, and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 7, 2003
    Publication date: January 15, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20030224197
    Abstract: In a solder that realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a connection portion between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: March 7, 2003
    Publication date: December 4, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Tetsuya Nakatsuka, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20030184986
    Abstract: A circuit board has a first electrode and a second electrode connected with respective electrodes of a chip and a first insulating layer with openings provided at respective positions corresponding to the first electrode and the second electrode. The openings of the first insulating layer are shaped so that the first insulating layer does not cover at least a region below the chip on the peripheral edges of the first and second electrodes.
    Type: Application
    Filed: February 20, 2003
    Publication date: October 2, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Masahide Okamoto, Syougo Senoo, Toshiyuki Kagami, Akihiro Sakashita
  • Patent number: 6563225
    Abstract: There is provided an electronic device comprising at least one electronic part and a substrate on which said electronic part is mounted, said electronic part and said substrate being bonded by a joint comprising a phase of Al particles and another phase of a Al—Mg—Ge—Zn alloy, said Al particles being connected to each other by said Al—Mg—Ge—Zn alloy phase.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: May 13, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Toshiharu Ishida, Kazuma Miura, Hanae Hata, Masahide Okamoto, Tetsuya Nakatsuka
  • Publication number: 20020149114
    Abstract: There is provided an electronic device comprising at least one electronic part and a substrate on which said electronic part is mounted, said electronic part and said substrate being bonded by a joint comprising a phase of Al particles and another phase of a Al—Mg—Ge—Zn alloy, said Al particles being connected to each other by said Al—Mg—Ge—Zn alloy phase.
    Type: Application
    Filed: February 27, 2002
    Publication date: October 17, 2002
    Inventors: Tasao Soga, Toshiharu Ishida, Kazuma Miura, Hanae Hata, Masahide Okamoto, Tetsuya Nakatsuka